Overview
The TMS320C6670ACYPA2 is a Multicore Fixed and Floating Point System-on-Chip (SoC) from Texas Instruments, part of the C66xx SoC family based on the KeyStone Multicore SoC Architecture. This device is designed for high-performance applications such as software-defined radio, emerging broadband, and other communications segments. It integrates four C66x CorePac DSPs, each operating at frequencies up to 1.2 GHz, providing a combined performance of up to 4.8 GHz. The platform is known for its power efficiency and ease of use, making it suitable for implementing multi-band, multi-standard waveforms and proprietary air-interfaces.
Key Specifications
| Specification | Details |
|---|---|
| Package | FCBGA (CYP) with 841 pins |
| Operating Temperature Range | -40°C to 100°C |
| Core Frequency | Up to 1.2 GHz |
| Performance | 153.6 GMAC/76.8 GFLOP @ 1.2GHz |
| Memory | 32KB L1P, 32KB L1D, 1024KB L2 per core; 2MB Shared L2 |
| Memory Interface | 64-Bit DDR3 Interface (DDR3-1600) - 8 GByte Addressable Memory Space |
| Interfaces | Four Lanes of SRIO 2.1, Two Lanes PCIe Gen2, HyperLink, Ethernet MAC Subsystem with two SGMII Ports |
| Other Features | Six Lane SerDes-Based Antenna Interface (AIF2), Hardware Coprocessors for Turbo Encoding/Decoding, Viterbi Decoders, FFT, Bit Rate CoProcessor, etc. |
Key Features
- Four TMS320C66x DSP Core Subsystems with frequencies up to 1.2 GHz.
- High-performance capabilities with 153.6 GMAC/76.8 GFLOP @ 1.2GHz.
- Advanced memory architecture including 32KB L1P, 32KB L1D, 1024KB L2 per core, and 2MB Shared L2.
- Multicore Navigator and TeraNet Switch Fabric for efficient data transfer.
- Network Coprocessors including Packet Accelerator and Security Accelerator.
- Multiple high-speed interfaces: SRIO 2.1, PCIe Gen2, HyperLink, and Ethernet MAC Subsystem.
- SerDes-Based Antenna Interface (AIF2) operating at up to 6.144 Gbps.
- Hardware Coprocessors for various tasks such as Turbo Encoding/Decoding, Viterbi Decoders, FFT, and more.
- I2C Interface, 16 GPIO Pins, SPI Interface, and eight 64-Bit Timers.
Applications
The TMS320C6670ACYPA2 is designed for high-performance applications in various sectors, including:
- Software-defined radio (SDR) systems.
- Emerging broadband and telecommunications.
- Multi-band, multi-standard wireless communication systems.
- Proprietary air-interface implementations.
- Other high-performance computing and signal processing tasks.
Q & A
- What is the TMS320C6670ACYPA2?
The TMS320C6670ACYPA2 is a Multicore Fixed and Floating Point System-on-Chip (SoC) from Texas Instruments.
- How many DSP cores does the TMS320C6670ACYPA2 have?
It has four TMS320C66x DSP Core Subsystems.
- What is the maximum operating frequency of the DSP cores?
The DSP cores can operate up to 1.2 GHz.
- What kind of memory does the TMS320C6670ACYPA2 support?
It supports 64-Bit DDR3 Interface (DDR3-1600) with 8 GByte addressable memory space.
- What high-speed interfaces are available on the TMS320C6670ACYPA2?
It includes SRIO 2.1, PCIe Gen2, HyperLink, and Ethernet MAC Subsystem with two SGMII Ports.
- Does the TMS320C6670ACYPA2 have hardware coprocessors?
Yes, it includes various hardware coprocessors for tasks such as Turbo Encoding/Decoding, Viterbi Decoders, FFT, and more.
- What is the operating temperature range of the TMS320C6670ACYPA2?
The operating temperature range is -40°C to 100°C.
- What package type does the TMS320C6670ACYPA2 use?
It uses an FCBGA (CYP) package with 841 pins.
- Is the TMS320C6670ACYPA2 backward compatible with other DSPs?
Yes, it is backward compatible with all existing C6000 family of fixed and floating point DSPs.
- What are some typical applications of the TMS320C6670ACYPA2?
It is used in software-defined radio, emerging broadband, telecommunications, and other high-performance signal processing tasks.
