Overview
The TMS320C6670ACYPA is a Multicore Fixed and Floating Point System on Chip (SoC) from Texas Instruments, part of the C66xx SoC family. It is based on TI's KeyStone Multicore SoC Architecture, designed for high-performance applications such as software-defined radio, emerging broadband, and other communications segments. The device integrates four TMS320C66x DSP Core Subsystems, each operating at frequencies of 1.0 to 1.2 GHz, enabling a combined performance of up to 4.8 GHz. This platform is highly integrated, power-efficient, and easy to use, making it ideal for implementing multi-band, multi-standard waveforms, including proprietary air-interfaces. The C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.
Key Specifications
| Parameter | Specification |
|---|---|
| Package | FCBGA (CYP) with 841 pins |
| Operating Temperature Range | -40°C to 100°C |
| Core Frequency | 1.0 GHz to 1.2 GHz |
| Performance | 153.6 GMAC/76.8 GFLOP @ 1.2GHz |
| L1 Cache | 32KB L1P, 32KB L1D per core |
| L2 Cache | 1024KB L2 per core, 2MB shared L2 |
| Memory Interface | 64-Bit DDR3 Interface (DDR3-1600), 8 GByte addressable memory space |
| Interconnects | Four lanes of SRIO 2.1, two lanes PCIe Gen2, HyperLink - 50Gbaud operation |
| Network Coprocessors | Packet Accelerator, Security Accelerator |
| Antenna Interface | Six lane SerDes-Based Antenna Interface (AIF2) - up to 6.144 Gbps |
| Timers and PLLs |
Key Features
- Four TMS320C66x DSP Core Subsystems at 1.0 GHz and 1.2 GHz
- High performance with 153.6 GMAC/76.8 GFLOP @ 1.2GHz
- Advanced cache hierarchy: 32KB L1P, 32KB L1D, 1024KB L2 per core, and 2MB shared L2
- Multicore Navigator and TeraNet Switch Fabric - 2 Tb
- Network Coprocessors: Packet Accelerator, Security Accelerator
- High-speed interconnects: Four lanes of SRIO 2.1, two lanes PCIe Gen2, HyperLink - 50Gbaud operation
- Ethernet MAC Subsystem with two SGMII ports supporting 10/100/1000 Mbps operation
- Hardware Coprocessors for turbo encoding, turbo decoding, Viterbi decoding, FFT, and more
- I2C Interface, 16 GPIO Pins, SPI Interface
Applications
The TMS320C6670ACYPA is designed for high-performance applications in various sectors, including:
- Software-defined radio
- Emerging broadband communications
- Multi-band, multi-standard wireless communication systems
- Proprietary air-interfaces
- Telecommunications infrastructure
Q & A
- What is the TMS320C6670ACYPA?
The TMS320C6670ACYPA is a Multicore Fixed and Floating Point System on Chip (SoC) from Texas Instruments, part of the C66xx SoC family.
- How many DSP cores does the TMS320C6670ACYPA have?
The device integrates four TMS320C66x DSP Core Subsystems.
- What are the operating frequencies of the DSP cores?
The DSP cores operate at frequencies of 1.0 to 1.2 GHz.
- What is the performance of the TMS320C6670ACYPA?
The device achieves 153.6 GMAC/76.8 GFLOP @ 1.2GHz.
- What type of memory interface does the TMS320C6670ACYPA support?
The device supports a 64-Bit DDR3 Interface (DDR3-1600) with an 8 GByte addressable memory space.
- What are the key interconnects available on the TMS320C6670ACYPA?
The device features four lanes of SRIO 2.1, two lanes PCIe Gen2, and HyperLink - 50Gbaud operation.
- Does the TMS320C6670ACYPA support any hardware coprocessors?
Yes, it includes hardware coprocessors for turbo encoding, turbo decoding, Viterbi decoding, FFT, and more.
- What are the typical applications of the TMS320C6670ACYPA?
The device is used in software-defined radio, emerging broadband communications, multi-band, multi-standard wireless communication systems, and proprietary air-interfaces.
- Is the TMS320C6670ACYPA backward compatible with other DSPs?
Yes, the C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.
- What is the operating temperature range of the TMS320C6670ACYPA?
The operating temperature range is -40°C to 100°C.
- What package type does the TMS320C6670ACYPA come in?
The device comes in a FCBGA (CYP) package with 841 pins.
