Overview
The TMS320C6670 Multicore Fixed and Floating Point System on Chip, produced by Texas Instruments, is a member of the C66xx SoC family. It is based on TI's KeyStone Multicore SoC Architecture, designed for high-performance applications such as software-defined radio, emerging broadband, and other communications segments. The C6670 integrates four TMS320C66x DSP Core Subsystems, each operating at 1.0 to 1.2 GHz, enabling a combined performance of up to 4.8 GHz. This platform is highly integrated, power-efficient, and easy to use, making it ideal for implementing multi-band, multi-standard waveforms, including proprietary air-interfaces. The C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.
Key Specifications
Specification | Details |
---|---|
Package | 841-FCBGA (24x24) |
Pins | 841 |
Operating Temperature Range | -40°C to 100°C |
Core Voltage | 1.00V |
I/O Voltage | 1.0V, 1.5V, 1.8V |
Clock Rate | 1.0 GHz to 1.2 GHz |
L1 Cache Per Core | 32KB L1P, 32KB L1D |
L2 Cache Per Core | 1024KB |
Shared L2 Cache | 2MB |
On-Chip RAM | 6.25MB |
Non-Volatile Memory | 128 kB ROM |
Interfaces | EBI/EMI, Ethernet MAC, PCIe, I²C, SPI, SRIO, UART |
Memory Interface | 64-Bit DDR3 Interface (DDR3-1600) - 8 GByte Addressable Memory Space |
Other Features | Four Lanes of SRIO 2.1, Two Lanes PCIe Gen2, HyperLink, Six Lane SerDes-Based Antenna Interface (AIF2), Hardware Coprocessors |
Key Features
- Four TMS320C66x DSP Core Subsystems at 1.00 GHz and 1.2GHz, enabling up to 4.8 GHz combined performance.
- High performance metrics: 153.6 GMAC/76.8 GFLOP @ 1.2GHz.
- Advanced cache hierarchy: 32KB L1P, 32KB L1D, 1024KB L2 per core, and 2MB shared L2.
- Multicore Navigator and TeraNet Switch Fabric - 2 Tb.
- Network Coprocessors: Packet Accelerator, Security Accelerator.
- High-speed interfaces: Four Lanes of SRIO 2.1, Two Lanes PCIe Gen2, HyperLink at 50Gbaud.
- Ethernet MAC Subsystem with two SGMII Ports supporting 10/100/1000 Mbps operation.
- Six Lane SerDes-Based Antenna Interface (AIF2) operating at up to 6.144 Gbps.
- Various hardware coprocessors for turbo encoding, turbo decoding, Viterbi decoding, FFT, and more.
- I2C Interface, 16 GPIO Pins, SPI Interface, and eight 64-Bit Timers.
Applications
The TMS320C6670 is designed for high-performance applications in various fields, including:
- Software-defined radio.
- Emerging broadband and other communications segments.
- Audio, speech, image, video, and bio-medical processing.
- Multi-band, multi-standard waveforms and proprietary air-interfaces.
Q & A
- What is the TMS320C6670?
The TMS320C6670 is a Multicore Fixed and Floating Point System on Chip from Texas Instruments, part of the C66xx SoC family.
- What is the clock rate of the TMS320C6670?
The clock rate of the TMS320C6670 is 1.0 GHz to 1.2 GHz per core.
- What kind of cache does the TMS320C6670 have?
The TMS320C6670 has 32KB L1P and 32KB L1D cache per core, 1024KB L2 cache per core, and 2MB shared L2 cache.
- What interfaces does the TMS320C6670 support?
The TMS320C6670 supports EBI/EMI, Ethernet MAC, PCIe, I²C, SPI, SRIO, and UART interfaces.
- What is the memory interface of the TMS320C6670?
The TMS320C6670 has a 64-Bit DDR3 Interface (DDR3-1600) with 8 GByte addressable memory space.
- What are the operating temperature ranges for the TMS320C6670?
The operating temperature range for the TMS320C6670 is -40°C to 100°C.
- Is the TMS320C6670 backward compatible with other DSPs?
Yes, the C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.
- What are some of the hardware coprocessors available on the TMS320C6670?
The TMS320C6670 includes hardware coprocessors for turbo encoding, turbo decoding, Viterbi decoding, FFT, and more.
- What is the package type of the TMS320C6670?
The TMS320C6670 comes in an 841-FCBGA (24x24) package.
- What are some typical applications of the TMS320C6670?
Typical applications include software-defined radio, emerging broadband, audio, speech, image, video, and bio-medical processing.