Overview
The TMS320C6670AXCYPA is a Multicore Fixed and Floating Point System on Chip (SoC) from Texas Instruments, part of the C66xx SoC family based on TI's KeyStone Multicore SoC Architecture. This device is designed for high-performance applications such as software-defined radio, emerging broadband, and other communications segments. It integrates four TMS320C66x DSP Core Subsystems, each operating at frequencies of 1.0 to 1.2 GHz, enabling a combined performance of up to 4.8 GHz. The platform is highly integrated, power-efficient, and easy to use, making it suitable for implementing multi-band, multi-standard waveforms, including proprietary air-interfaces.
Key Specifications
| Parameter | Specification |
|---|---|
| Package | 841-BFBGA, FCBGA (24x24) |
| Pins | 841 |
| Operating Temperature Range | -40°C to 100°C |
| Clock Rate | 1.0 GHz to 1.2 GHz |
| Non-Volatile Memory | ROM (128 kB) |
| On-Chip RAM | 6.25 MB |
| Voltage - I/O | 1.0V, 1.5V, 1.8V |
| Voltage - Core | 1.00V |
| Interface | EBI/EMI, Ethernet MAC, PCIe, I²C, SPI, SRIO, UART |
| Memory Interface | 64-Bit DDR3 Interface (DDR3-1600) - 8 GByte Addressable Memory Space |
| Antenna Interface | Six Lane SerDes-Based Antenna Interface (AIF2) - Operating at up to 6.144 Gbps |
Key Features
- Four TMS320C66x DSP Core Subsystems at 1.0 GHz and 1.2 GHz
- 153.6 GMAC/76.8 GFLOP @ 1.2 GHz
- 32KB L1P, 32KB L1D, 1024KB L2 Per Core; 2MB Shared L2
- Multicore Navigator and TeraNet Switch Fabric - 2 Tb
- Network Coprocessors: Packet Accelerator, Security Accelerator
- Four Lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex
- Two Lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex
- HyperLink - 50Gbaud Operation, Full Duplex
- Ethernet MAC Subsystem - Two SGMII Ports w/ 10/100/1000 Mbps operation
- Hardware Coprocessors:
- Enhanced Coprocessor for Turbo Encoding
- Three Enhanced Coprocessors for Turbo Decoding
- Four Viterbi Decoders
- Three Fast Fourier Transform Coprocessors
- Bit Rate CoProcessor
- Two Receiver Accelerators for WCDMA
- Transmit Accelerator for WCDMA
- Four Rake Search Accelerators for Chip Rate Processing and Reed-Muller Decoding
- I2C Interface, 16 GPIO Pins, SPI Interface
- Eight 64-Bit Timers, Three On-Chip PLLs
Applications
The TMS320C6670AXCYPA is designed for various high-performance applications, including:
- Software-defined radio
- Emerging broadband communications
- Multi-band, multi-standard waveforms
- Proprietary air-interfaces
Q & A
- What is the TMS320C6670AXCYPA?
The TMS320C6670AXCYPA is a Multicore Fixed and Floating Point System on Chip (SoC) from Texas Instruments.
- What is the clock rate of the TMS320C6670AXCYPA?
The clock rate of the TMS320C6670AXCYPA is 1.0 GHz to 1.2 GHz.
- How many DSP cores does the TMS320C6670AXCYPA have?
The TMS320C6670AXCYPA has four TMS320C66x DSP Core Subsystems.
- What type of memory interface does the TMS320C6670AXCYPA support?
The TMS320C6670AXCYPA supports a 64-Bit DDR3 Interface (DDR3-1600) with 8 GByte addressable memory space.
- What are the key interfaces supported by the TMS320C6670AXCYPA?
The key interfaces include EBI/EMI, Ethernet MAC, PCIe, I²C, SPI, SRIO, and UART.
- What is the operating temperature range of the TMS320C6670AXCYPA?
The operating temperature range is -40°C to 100°C.
- What are the hardware coprocessors available on the TMS320C6670AXCYPA?
The hardware coprocessors include Enhanced Coprocessor for Turbo Encoding, Turbo Decoding, Viterbi Decoders, Fast Fourier Transform Coprocessors, Bit Rate CoProcessor, and others.
- Is the TMS320C6670AXCYPA backward compatible with other DSPs?
Yes, the C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.
- What is the package type of the TMS320C6670AXCYPA?
The package type is 841-BFBGA, FCBGA (24x24).
- What are the primary applications of the TMS320C6670AXCYPA?
The primary applications include software-defined radio, emerging broadband communications, and multi-band, multi-standard waveforms.
