Overview
The TMS320C6670AXCYP2 is a member of the TMS320C66xx family of multicore Digital Signal Processors (DSPs) from Texas Instruments. This System on Chip (SoC) is based on TI's KeyStone Multicore SoC Architecture, designed for high-performance applications such as software-defined radio, emerging broadband, and other communications segments. The device integrates four TMS320C66x DSP Core Subsystems, each operating at frequencies up to 1.2 GHz, providing a combined processing power of up to 4.8 GHz. This architecture ensures high integration, power efficiency, and ease of use for implementing multi-band, multi-standard waveforms, including proprietary air-interfaces.
Key Specifications
Specification | Details |
---|---|
Package | 841-BFBGA, FCBGA |
Pins | 841 |
Operating Temperature Range | 0°C to 100°C (TC) |
Voltage - Core | 1.00V |
Voltage - I/O | 1.0V, 1.5V, 1.8V |
Clock Rate | Up to 1.2 GHz |
Non-Volatile Memory | ROM (128 kB) |
On-Chip RAM | 6.25 MB |
Memory Interface | 64-Bit DDR3 Interface (DDR3-1600), up to 8 GByte addressable memory space |
Interfaces | EBI/EMI, Ethernet MAC, PCIe, I2C, SPI, SRIO, UART |
Other Features | Four lanes of SRIO 2.1, two lanes PCIe Gen2, HyperLink, Ethernet MAC subsystem with two SGMII ports, six lane SerDes-based antenna interface (AIF2) |
Key Features
- Four TMS320C66x DSP Core Subsystems at 1.00 GHz and 1.2 GHz, providing up to 4.8 GHz combined processing power.
- High performance with 153.6 GMAC/76.8 GFLOP @ 1.2 GHz.
- Memory architecture includes 32KB L1P, 32KB L1D, 1024KB L2 per core, and 2MB shared L2.
- Multicore Navigator and TeraNet Switch Fabric for efficient data flow.
- Network Coprocessors including Packet Accelerator and Security Accelerator.
- Hardware coprocessors for turbo encoding, turbo decoding, Viterbi decoding, FFT, and other functions.
- Multiple high-speed interfaces: SRIO 2.1, PCIe Gen2, HyperLink, and Ethernet MAC subsystem.
- Six lane SerDes-based antenna interface (AIF2) operating at up to 6.144 Gbps.
- I2C, SPI, and UART interfaces, along with 16 GPIO pins and eight 64-bit timers).
Applications
The TMS320C6670AXCYP2 is designed for various high-performance applications, including:
- Software-defined radio and other wireless communication systems.
- Emerging broadband and communications segments.
- Test and measurement equipment).
- Mission-critical systems).
- Industrial automation and control systems).
- Medical and high-end imaging equipment).
- High-performance computing and data processing).
Q & A
- What is the TMS320C6670AXCYP2?
The TMS320C6670AXCYP2 is a multicore Digital Signal Processor (DSP) from Texas Instruments, part of the TMS320C66xx family, designed for high-performance applications.
- How many DSP cores does the TMS320C6670AXCYP2 have?
The device has four TMS320C66x DSP Core Subsystems.
- What are the operating frequencies of the DSP cores?
The DSP cores operate at frequencies up to 1.2 GHz.
- What is the memory architecture of the TMS320C6670AXCYP2?
The memory architecture includes 32KB L1P, 32KB L1D, 1024KB L2 per core, and 2MB shared L2.
- What high-speed interfaces does the TMS320C6670AXCYP2 support?
The device supports SRIO 2.1, PCIe Gen2, HyperLink, and Ethernet MAC subsystem.
- What are some of the hardware coprocessors available on the TMS320C6670AXCYP2?
The device includes hardware coprocessors for turbo encoding, turbo decoding, Viterbi decoding, FFT, and other functions.
- What is the operating temperature range of the TMS320C6670AXCYP2?
The operating temperature range is from 0°C to 100°C (TC).
- What type of memory interface does the TMS320C6670AXCYP2 have?
The device has a 64-Bit DDR3 Interface (DDR3-1600) with up to 8 GByte addressable memory space.
- What are some typical applications of the TMS320C6670AXCYP2?
Typical applications include software-defined radio, emerging broadband, test and measurement, mission-critical systems, industrial automation, medical and high-end imaging equipment, and high-performance computing.
- What is the package type of the TMS320C6670AXCYP2?
The device is packaged in a 841-BFBGA, FCBGA.