Overview
The SPC560P50L3B1ABR is a 32-bit system-on-chip (SoC) automotive microcontroller from STMicroelectronics. It is part of the SPC560 series, designed to address various automotive applications, particularly in chassis control systems such as electrical hydraulic power steering (EHPS) and electric power steering (EPS), as well as airbag systems. This microcontroller is built on the e200z0h CPU core complex, which operates at a frequency of up to 64 MHz and is compliant with the Power Architecture embedded category.
Key Specifications
| Parameter | Specification |
|---|---|
| CPU Core | 64 MHz, single issue, 32-bit e200z0h |
| Memory | Up to 512 KB on-chip code flash memory with ECC, 64 KB on-chip data flash memory with ECC, up to 40 KB on-chip SRAM with ECC |
| Package | LQFP 100 (14x14x1.4 mm) |
| Operating Temperature | -40°C to 105°C |
| Voltage Supply | 4.5 V ~ 5.5 V |
| Number of I/O | 67 |
| Communication Interfaces | 2 LINFlex channels, 4 DSPI channels, 1 FlexCAN interface, 1 safety port based on FlexCAN, 1 FlexRay module |
| Analog-to-Digital Converters (ADC) | 2 × 10-bit ADCs with 26 input channels |
| Timers | 6 timers with up/down count capabilities, 16-bit resolution, cascadable counters, quadrature decode with rotation direction flag |
| Other Features | Programmable watchdog timer, non-maskable interrupt, fault collection unit, Nexus L2+ interface, 16-channel eDMA controller |
Key Features
- Compliant with Power Architecture embedded category and Variable Length Encoding (VLE)
- Fail-safe protection and programmable watchdog timer
- Non-maskable interrupt and fault collection unit
- Nexus L2+ interface and 16-channel eDMA controller
- General purpose I/Os individually programmable as input, output or special function
- 2 general purpose eTimer units and 6 timers with up/down count capabilities
- Quadrature decode with rotation direction flag and double buffer input capture and output compare
- Communications interfaces including LINFlex, DSPI, FlexCAN, and FlexRay
- Two 10-bit analog-to-digital converters (ADC) with programmable ADC Cross Triggering Unit (CTU)
- On-chip CAN/UART bootstrap loader with Boot Assist Module (BAM)
- FlexPWM unit with 8 complementary or independent outputs and ADC synchronization signals
Applications
The SPC560P50L3B1ABR is designed for various automotive applications, including:
- Electrical Hydraulic Power Steering (EHPS)
- Electric Power Steering (EPS)
- Airbag systems
- Other chassis control systems
Q & A
- What is the CPU core of the SPC560P50L3B1ABR?
The CPU core is a 64 MHz, single issue, 32-bit e200z0h.
- What is the memory configuration of the SPC560P50L3B1ABR?
It includes up to 512 KB on-chip code flash memory, 64 KB on-chip data flash memory, and up to 40 KB on-chip SRAM, all with ECC.
- What is the package type of the SPC560P50L3B1ABR?
The package type is LQFP 100 (14x14x1.4 mm).
- What is the operating temperature range of the SPC560P50L3B1ABR?
The operating temperature range is -40°C to 105°C.
- What communication interfaces does the SPC560P50L3B1ABR support?
It supports 2 LINFlex channels, 4 DSPI channels, 1 FlexCAN interface, 1 safety port based on FlexCAN, and 1 FlexRay module.
- How many analog-to-digital converters (ADCs) does the SPC560P50L3B1ABR have?
It has 2 × 10-bit ADCs with 26 input channels.
- What are the key features of the timers in the SPC560P50L3B1ABR?
The timers have up/down count capabilities, 16-bit resolution, are cascadable, and include quadrature decode with rotation direction flag.
- Does the SPC560P50L3B1ABR have any fail-safe and watchdog features?
Yes, it includes fail-safe protection and a programmable watchdog timer.
- What is the purpose of the Nexus L2+ interface in the SPC560P50L3B1ABR?
The Nexus L2+ interface is used for debugging and testing purposes.
- What are the typical applications of the SPC560P50L3B1ABR?
It is typically used in electrical hydraulic power steering (EHPS), electric power steering (EPS), airbag systems, and other chassis control systems.
