Overview
The NB3W800LMNG, produced by onsemi, is a low-power 8-output differential buffer designed to meet the performance requirements of the DB800ZL specification. This component is optimized for distributing reference clocks in various high-speed applications, including Intel® QuickPath Interconnect (QPI and UPI), PCIe Gen1/Gen2/Gen3/Gen4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI). It features a fixed, internal feedback path to maintain low drift, which is critical for QPI applications.
Key Specifications
| Parameter | Value | Units |
|---|---|---|
| Supply Voltage (VDD) | 3.3 V ± 5% | V |
| Output Frequency | 100 MHz or 133 MHz | Hz |
| Output Type | 8 Differential Clock Output Pairs @ 0.7 V | |
| Cycle-to-Cycle Jitter | < 50 ps | ps |
| Output-to-Output Skew | < 50 ps | ps |
| Input-to-Output Delay Variation | < 100 ps | ps |
| PCIe Phase Jitter (Gen3) | < 1.0 ps RMS | ps |
| PCIe Phase Jitter (Gen4) | < 0.5 ps RMS | ps |
| QPI 9.6GT/s 12UI Phase Jitter | < 0.2 ps RMS | ps |
| Package Type | QFN48 (Pb-Free) | |
| Operating Temperature | 0°C to 70°C | °C |
| Storage Temperature | −65°C to 150°C | °C |
Key Features
- Low-power NMOS Push-Pull HCSL Compatible Outputs
- PLL Configurable for PLL Mode or Bypass Mode (Fanout Operation)
- Selectable PLL Bandwidth; Minimizes Jitter Peaking in Downstream PLL’s
- SMBus Programmable Configurations
- Spread Spectrum Compatible; Tracks Input Clock Spreading for Low EMI
- Individual OE Control; Hardware Control of Each Output
- Pseudo-External Fixed Feedback for Lowest Input-to-Output Delay
- Supports PCIe, QPI, and UPI Applications
Applications
- Intel® QuickPath Interconnect (QPI and UPI)
- PCIe Gen1/Gen2/Gen3/Gen4
- SAS and SATA
- Intel Scalable Memory Interconnect (Intel SMI)
Q & A
- What is the primary function of the NB3W800LMNG?
The NB3W800LMNG is a low-power 8-output differential buffer designed to distribute reference clocks in high-speed applications.
- What are the supported output frequencies?
The device supports output frequencies of 100 MHz or 133 MHz.
- What is the significance of the internal feedback path?
The fixed, internal feedback path maintains low drift, which is critical for QPI applications.
- How is the output frequency selected?
The output frequency is selected using the 100M_133M# hardware pin with an external pull-up or pull-down resistor.
- What is the role of the PWRGD/PWRDN# pin?
The PWRGD/PWRDN# pin is used to sample initial configurations and to shut off all clocks cleanly, invoking power savings mode when de-asserted low.
- Can the outputs be individually controlled?
Yes, each output can be individually enabled or disabled by SMBus control register bits and dedicated OE# pins.
- Is the device compatible with spread spectrum clocking?
Yes, the device is spread spectrum compatible and tracks input clock spreading for low EMI.
- What is the operating temperature range of the device?
The device operates within a temperature range of 0°C to 70°C.
- What is the package type of the NB3W800LMNG?
The device is packaged in a QFN48 (Pb-Free) package.
- Is the device scheduled for obsolescence?
Yes, the NB3W800LMNG is scheduled for obsolescence and will be discontinued by the manufacturer.
