Overview
The NB3W800LMNTXG, produced by onsemi, is a low-power 8-output differential buffer designed to meet the performance requirements of various high-speed clock distribution applications. This device is compatible with HCSL (High-Speed Current Steering Logic) and supports frequencies up to 133.33 MHz, making it suitable for use in PCIe Gen1/Gen2/Gen3/Gen4, Intel QuickPath Interconnect (QPI and UPI), SAS, SATA, and Intel Scalable Memory Interconnect (SMI) environments.
Key Specifications
| Parameter | Min | Max | Units | |
|---|---|---|---|---|
| Supply Voltage (VDD) | 3.0 | 3.3 | 3.6 | V |
| Operating Temperature | 0 | - | 70 | °C |
| Output Frequency (Max) | - | - | 133.33 | MHz |
| Cycle-to-Cycle Jitter | - | - | 50 | ps |
| Output-to-Output Skew | - | - | 50 | ps |
| Input-to-Output Delay Variation | - | - | 100 | ps |
| PCIe Phase Jitter (Gen3) | - | - | 1.0 | ps RMS |
| PCIe Phase Jitter (Gen4) | - | - | 0.5 | ps RMS |
| QPI 9.6GT/s 12UI Phase Jitter | - | - | 0.2 | ps RMS |
| Package Type | - | - | QFN-48 (6x6) | - |
Key Features
- 8 differential clock output pairs at 0.7 V, compatible with HCSL outputs
- Low-power NMOS push-pull outputs
- Cycle-to-cycle jitter < 50 ps and output-to-output skew < 50 ps
- PLL configurable for PLL mode or bypass mode (fanout operation)
- Supports 100 MHz or 133 MHz PLL mode operation for PCIe, QPI, and UPI applications
- Selectable PLL bandwidth to minimize jitter peaking in downstream PLLs
- SMBus programmable configurations
- Spread spectrum compatible, tracking input clock spreading for low EMI
- Individual OE control; hardware control of each output
- Pseudo-external fixed feedback for lowest input-to-output delay
Applications
- PCIe Gen1/Gen2/Gen3/Gen4 applications
- Intel QuickPath Interconnect (QPI and UPI)
- SAS and SATA interfaces
- Intel Scalable Memory Interconnect (SMI)
- High-speed clock distribution in data centers and cloud infrastructure
- Server and storage systems requiring precise clock signals
Q & A
- What is the maximum output frequency of the NB3W800LMNTXG?
The maximum output frequency is 133.33 MHz.
- What types of interfaces does the NB3W800LMNTXG support?
The device supports PCIe Gen1/Gen2/Gen3/Gen4, Intel QPI and UPI, SAS, SATA, and Intel SMI.
- What is the typical power consumption of the NB3W800LMNTXG at 133 MHz?
The typical power consumption is around 105 mA for the VDD rail and 40 mA for the VDDA + VDDR rail at 133 MHz.
- How does the device manage jitter?
The device features selectable PLL bandwidth to minimize jitter peaking in downstream PLLs and has phase jitter specifications for PCIe Gen3 and Gen4, as well as QPI applications.
- What is the package type of the NB3W800LMNTXG?
The device is packaged in a QFN-48 (6x6) package.
- Can the outputs be individually controlled?
Yes, each output can be individually enabled or disabled by SMBus control register bits and dedicated OE# pins.
- Is the device compatible with spread spectrum clocking?
Yes, the device is spread spectrum compatible and tracks input clock spreading for low EMI.
- What is the operating temperature range of the NB3W800LMNTXG?
The operating temperature range is from 0°C to 70°C.
- How is the power-down mode managed?
The PWRGD/PWRDN# pin can be used to shut off all clocks cleanly and invoke power savings mode.
- What is the significance of the 100M_133M# pin?
The 100M_133M# pin is used for frequency selection, allowing the user to choose between 100 MHz and 133 MHz output frequencies.
