ST Makes Its Foray Into Silicon Photonic ICs for Data Center Interconnects
STMicroelectronics is venturing into silicon photonics for the first time with its new PIC100 platform. ST designed the platform to improve the performance and efficiency of optical interconnects in data centers and AI infrastructure. As such, it integrates silicon photonics (SiPho) and BiCMOS technology to deliver high bandwidth, low energy consumption, and extended reach for next-generation optical transceivers.
ST’s PIC100.
All About Circuits was briefed by Vincent Fraisse, general manager of the RF and communication division at STMicroelectronics, to learn about the new ICs firsthand.
Silicon Photonics and BiCMOS: A Synergistic Approach
The PIC100 platform is a 300-mm silicon photonics solution that leverages ST’s expertise in BiCMOS technology to enhance signal processing for optical interconnects. According to the company, integrating silicon photonics with BiCMOS enables a direct, high-performance electro-optical conversion process for next-generation AI and cloud data center connectivity. Unlike traditional EML and VCSEL-based interconnect solutions, PIC100 achieves 200 Gbps per lane using a pure-silicon platform, making it a scalable and efficient alternative to legacy technologies.
“PIC100 is today the only silicon-only 300-millimeter technology able to support up to 200 gigabits per connection lane, equivalent to 100 gigabits in PAM4—hence the name, PIC100,” Fraisse explained.
ST’s BiCMOS technology.
ST claims that its BiCMOS B55X process brings industry-leading linearity, high-frequency performance, and low-noise amplification to electro-optical circuits. For example, the BiCMOS implementation supports high-speed transimpedance amplifiers (TIAs) and laser drivers that maximize signal integrity and efficiency, even at 200 Gbps per lane. The BiCMOS B55X process is particularly well-suited for linear pluggable optics (LPO) and linear receiver optics (LRO), which eliminate the need for DSP-based equalization and further reduce power consumption and latency.
Integration and Manufacturability
ST manufactured this platform on 300-mm wafers to ensure greater process uniformity, higher yield, and cost-efficiency for large-scale production. The company used advanced immersion lithography at its Crolles, France, facility to achieve best-in-class wafer uniformity and digital-CMOS-class yield performance. The high-density integration of silicon photonics components—including modulators, photodetectors, and waveguides—within a single chip significantly enhances performance while reducing system complexity.
Inside a PIC100.
The PIC100 also notably uses an edge coupler for fiber attachment. Traditional grating couplers, while easier to align during testing, introduce higher optical losses due to mode mismatch and scattering effects.
“Thanks to an innovative material stack up, PIC100 will also enable the attachment of the fiber to the edge of the photonic IC, thus reducing system losses—a constant challenge for any transceiver developer,” Fraisse said.
By adopting an edge coupler design, the PIC100 achieves lower coupling losses of less than 1.5 dB, resulting in improved link efficiency and longer reach compared to traditional optical transceivers.
The Dawn of ST's Silicon Photonics Age
Data center operators are more readily adopting silicon photonics for interconnects, with hyperscalers and optical module manufacturers moving toward integrated photonic solutions. AWS partnered with ST to develop the PIC100, with plans to deploy the technology in AWS' infrastructure as it reaches production readiness.
“We have signed a collaboration agreement with AWS, who's been intimately involved in the development of PIC100 and will deploy this technology in their infrastructure as it reaches the production stage later this year,” Fraisse said.
While PIC100 is ST’s first commercial silicon photonics solution, the company has outlined a roadmap to extend its capabilities. Future iterations will include support for 400 Gbps per lane and the integration of advanced materials, such as germanium silicon photodetectors and hybrid III-V semiconductor lasers, to enhance efficiency and performance.
Additionally, ST plans to introduce TSV-integrated optical interconnects to facilitate direct chip-to-chip optical communication. By eliminating PCB traces and copper interconnects, silicon photonics-based optical I/O will allow AI accelerators and compute clusters to scale in density set, thereby accelerating the adoption of silicon photonics in hyperscale and AI infrastructures.
Ramp-up is targeted for the second half of 2025.
