Boost Your FPGA Development With Libero® SoC Design Suite v2024.2: New Features, Capabilities and Device Support

Microchip's Libero SoC v2024.2 introduces major upgrades, making it a must-have for FPGA design engineers focused on performance, runtime optimization, efficiency and new device support. Here's a deep dive into what makes this version stand out.

Expanded Device Support

Libero SoC Design Suite v2024.2 significantly extends support to include new devices like radiation-rolerant PolarFire® System-on-Chip Field-Programmable Gate Arrays (SoC FPGAs) for those working in critical applications like aerospace, defense and space applications. With the release of MPFS250T, engineers now have access to automotive grade production devices tailored for high-performance, low-power applications, enabling more flexibility in FPGA design.

Moreover, the update integrates enhanced support for RT PolarFire SoC devices, expanding its capabilities for radiation-tolerant systems, especially relevant in high-reliability markets. These devices are known for their impressive performance in harsh environments, further boosting their appeal to sectors like defense and space. By including these advanced devices, Libero SoC Design Suite v2024.2 enhances the designer’s toolkit, offering an integrated approach to developing resilient, low-power systems with improved security and reliability.

Performance Enhancements

Libero SoC Design Suite 2024.2 isn’t just about new device support—it’s also about optimizing performance across the board. Notably, enhancements to timing analysis deliver faster timing closure, which is critical for ensuring that high-performance designs meet rigorous timing constraints. The place-and-route algorithms have been refined, providing better utilization and reduced runtimes. Engineers will now experience faster compilation times, which is essential for speeding up iterative design processes, resulting in quicker turnaround times.

Additionally, improvements in FSM (Finite State Machine) error correction with Hamming distance encoding ensure that design logic is more resilient to errors. This means your design is better protected against faults, adding an extra layer of robustness without compromising on performance.

Boost FPGA performance and efficiency with SmartHLS™ compiler: generate look-up table values from user C++ code while the new Open-Source Libraries—featuring FFT, Gamma Correction and more—accelerate your development and shorten time to market.

Improve User Experience

The latest advancements in SmartHLS compiler and Libero SoC Design Suite v2024.2 significantly enhance the user experience by creating a seamless, unified workflow. SmartHLS compiler now supports all operating systems compatible with Libero, allowing users to enjoy a consistent experience across platforms. With a single license covering both Libero SoC Design Suite and SmartHLS compiler, engineers can eliminate the hassle of managing multiple licenses, streamlining their workflow without the added overhead. Additionally, SmartHLS compiler facilitates multiple instances of the same HLS-generated HDL+ component within Libero SoC Design Suite, promoting efficiency and reusability. The integration of on-chip Identify instrumentation inputs and outputs automatically into Libero SoC Design Suite designs saves users valuable time, while the introduction of real-time FIFO occupancy monitoring for SmartHLS compiler designs provides instant visibility into performance metrics. Together, these enhancements create a more efficient and user-friendly environment, empowering engineers to focus on innovation and design excellence.

Streamlined DDR4/DDR3 Support and Silicon Features

The release also improves DDR4 and DDR3 memory support, especially in terms of training and calibration. These memory interfaces are crucial for applications requiring high bandwidth, and the enhanced support in Libero v2024.2 makes it easier to configure and debug memory-related issues, allowing designers to build more reliable systems.

New silicon features introduced in this version include better handling of memory initialization sequences, power-up sequences and calibration mechanisms, giving engineers the tools they need to optimize memory performance and ensure stable operation in demanding environments.

Simulation and Debug Tools

Simulation and debugging are vital parts of the FPGA design process, and Libero SoC Design Suite v2024.2 strengthens these capabilities with upgraded integration for the latest ModelSim and QuestaSim Pro simulation tools. These upgrades offer better debug visibility, allowing engineers to identify and resolve issues early in the design cycle. With more powerful verification environments, engineers can achieve higher confidence in their designs, reducing the risk of costly errors later in production.

In addition to enhanced simulation capabilities, FlashPro 6 now supports ISSI Flash programming, expanding the suite’s programming flexibility. Engineers can now benefit from streamlined device programming, making the development process even more efficient.

Improved Documentation and Licensing Flexibility

The 2024.2 version brings better documentation and clearer guidelines, especially for Linux and Windows operating systems, ensuring that engineers have comprehensive resources to help troubleshoot and optimize their workflows. The upgrade also introduces 64-bit licensing daemons, which allow for a smoother integration experience, making it easier to manage licenses and avoid common activation issues.

In today’s FPGA landscape, licensing flexibility can make or break your workflow. With the updated 64-bit support, engineers can expect smoother transitions across tools, ensuring that they can focus on their designs rather than worrying about licensing constraints.

Conclusion

Libero SoC Design Suite v2024.2 represents a leap forward for FPGA design engineers. Whether you’re working on advanced defense systems, automotive-grade solutions or high-performance embedded designs, the added device support, enhanced memory capabilities, faster runtimes and improved simulation tools provide everything needed for next-generation FPGA development.