Overview
The TMS320C6711DGDP200 is a high-performance floating-point Digital Signal Processor (DSP) from Texas Instruments, part of the TMS320C6000 DSP platform. This device is based on the advanced very-long-instruction-word (VLIW) architecture, making it an excellent choice for multichannel and multifunction applications. The C6711D offers significant performance with up to 1200 million floating-point operations per second (MFLOPS) at a clock rate of 200 MHz and up to 1500 MFLOPS at 250 MHz. It combines the operational flexibility of high-speed controllers with the numerical capability of array processors, making it a cost-effective solution for high-performance DSP programming challenges.
Key Specifications
| Parameter | Specification |
|---|---|
| Clock Rates | 167 MHz, 200 MHz, 250 MHz |
| Instruction Cycle Time | 6 ns (167 MHz), 5 ns (200 MHz), 4 ns (250 MHz) |
| Performance | Up to 1200 MFLOPS (200 MHz), up to 1500 MFLOPS (250 MHz) |
| Functional Units | Eight highly independent functional units: four floating-/fixed-point ALUs, two fixed-point ALUs, two floating-/fixed-point multipliers |
| General-Purpose Registers | 32 registers of 32-bit word length |
| Cache Architecture | Level 1 program cache (L1P): 32-Kbit direct mapped cache; Level 1 data cache (L1D): 32-Kbit 2-way set-associative cache; Level 2 memory/cache (L2): 512-Kbit unified mapped RAM/cache |
| Peripherals | Two multichannel buffered serial ports (McBSPs), two general-purpose timers, host-port interface (HPI), glueless external memory interface (EMIF) |
| Package | 272-Pin Ball Grid Array (BGA) |
| Process Technology | 0.13 µm CMOS technology |
| Voltage | Core: 1.20 V or 1.4 V; I/O: 3.3 V |
Key Features
- High-Performance VLIW Architecture: Supports up to eight 32-bit instructions per cycle.
- Advanced Functional Units: Includes four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers.
- Cache and Memory: Two-level cache-based architecture with 32-Kbit L1P and L1D caches and a 512-Kbit L2 unified mapped RAM/cache.
- Peripheral Set: Features two McBSPs, two general-purpose timers, an HPI, and a glueless EMIF for interfacing with various memory types.
- Development Tools: Includes a new C compiler, an assembly optimizer, and a Windows debugger interface for efficient programming and debugging.
- Flexible Clock Generator: PLL-based clock generator module with prescaler, multiplier, and postscaler options.
- GPIO Module: Dedicated general-purpose input/output module with 5 pins.
- JTAG Compatibility: IEEE-1149.1 (JTAG) boundary-scan-compatible.
Applications
The TMS320C6711DGDP200 is suitable for a wide range of applications that require high-performance digital signal processing, including:
- Telecommunications: Supports interfaces like T1/E1, MVIP, and SCSA framers.
- Audio and Video Processing: Ideal for real-time audio and video processing due to its high MFLOPS performance.
- Medical Imaging: Can be used in medical imaging applications requiring intensive numerical computations.
- Industrial Automation: Suitable for control and monitoring systems in industrial environments.
- Radar and Sonar Systems: Can handle complex signal processing tasks in radar and sonar systems.
Q & A
- What is the clock rate range of the TMS320C6711DGDP200?
The clock rate range is 167 MHz, 200 MHz, and 250 MHz.
- What is the performance of the TMS320C6711DGDP200 in terms of MFLOPS?
It offers up to 1200 MFLOPS at 200 MHz and up to 1500 MFLOPS at 250 MHz.
- How many functional units does the TMS320C6711DGDP200 have?
It has eight highly independent functional units.
- What type of cache architecture does the TMS320C6711DGDP200 use?
It uses a two-level cache-based architecture with L1P, L1D, and L2 caches.
- What peripherals are included in the TMS320C6711DGDP200?
It includes two McBSPs, two general-purpose timers, an HPI, and a glueless EMIF.
- What is the package type of the TMS320C6711DGDP200?
It is packaged in a 272-Pin Ball Grid Array (BGA).
- What is the process technology used in the TMS320C6711DGDP200?
It uses 0.13 µm CMOS technology.
- What are the voltage requirements for the TMS320C6711DGDP200?
The core voltage is 1.20 V or 1.4 V, and the I/O voltage is 3.3 V.
- Is the TMS320C6711DGDP200 JTAG compatible?
Yes, it is IEEE-1149.1 (JTAG) boundary-scan-compatible.
- What development tools are available for the TMS320C6711DGDP200?
It includes a new C compiler, an assembly optimizer, and a Windows debugger interface.
