Overview
The DS90LV001TLD, manufactured by Texas Instruments, is an LVDS-LVDS Buffer designed to enhance system performance in large-scale systems. It takes an LVDS input signal and provides an LVDS output signal, addressing the issue of signal degradation due to long stub lengths between transmission lines and receivers on individual cards. This component is particularly useful in scenarios where signals are distributed across backplanes, and shortening the distance between the transmission line and the receiver is crucial for optimal system speed.
Key Specifications
| Specification | Value |
|---|---|
| Package | 8-pin WSON, 8-pin SOIC |
| Pins | 8 |
| Operating Temperature Range (°C) | -40 to 85 |
| Supply Voltage | Single +3.3 V |
| Input Signal Type | LVDS, LVPECL |
| Output Signal Type | LVDS |
| Transmission Data Rate | 800 Mbps |
| Propagation Delay | 1.4 ns (Typ) |
| Peak-to-Peak Jitter | 100 ps (Typ) with PRBS = 2^23-1 Data Pattern at 800 Mbps |
| Receiver Input Threshold | < ±100 mV |
| Compliance | ANSI/TIA/EIA-644-A LVDS Standard |
Key Features
- Single +3.3 V Supply
- LVDS Receiver Inputs Accept LVPECL Signals
- TRI-STATE Outputs with Output Enable Pin
- Fast Propagation Delay of 1.4 ns (Typ)
- Low Jitter 800 Mbps Fully Differential Data Path
- 100 ps (Typ) of pk-pk Jitter with PRBS = 2^23-1 Data Pattern at 800 Mbps
- Compatible with ANSI/TIA/EIA-644-A LVDS Standard
- Space Saving (70%) WSON Package and 8-pin SOIC Package
- Industrial Temperature Range
Applications
The DS90LV001TLD is ideal for use in large systems where signal distribution across backplanes is necessary. It is particularly useful in applications requiring high-speed data transmission with minimal signal degradation, such as in telecommunications, data centers, and high-performance computing systems. The component can also serve as an LVPECL-LVDS translator due to its wide input dynamic range, making it versatile for various interface needs.
Q & A
- What is the primary function of the DS90LV001TLD?
The DS90LV001TLD is an LVDS-LVDS Buffer that takes an LVDS input signal and provides an LVDS output signal, helping to improve system performance by reducing signal degradation due to long stub lengths. - What are the available package options for the DS90LV001TLD?
The component is available in 8-pin WSON and 8-pin SOIC packages. - What is the operating temperature range of the DS90LV001TLD?
The operating temperature range is -40°C to 85°C. - What is the supply voltage requirement for the DS90LV001TLD?
The component operates on a single +3.3 V supply. - Can the DS90LV001TLD accept LVPECL signals?
Yes, the LVDS receiver inputs can accept LVPECL signals. - What is the typical propagation delay of the DS90LV001TLD?
The typical propagation delay is 1.4 ns. - What is the peak-to-peak jitter of the DS90LV001TLD at 800 Mbps?
The peak-to-peak jitter is 100 ps (Typ) with PRBS = 2^23-1 Data Pattern at 800 Mbps. - Is the DS90LV001TLD compliant with any industry standards?
Yes, it is compliant with the ANSI/TIA/EIA-644-A LVDS Standard. - What is the purpose of the output enable pin on the DS90LV001TLD?
The output enable pin allows the user to place the LVDS output in TRI-STATE. - In what types of applications is the DS90LV001TLD commonly used?
The component is commonly used in telecommunications, data centers, and high-performance computing systems where high-speed data transmission with minimal signal degradation is required.
