Overview
The CDCM61002RHBR from Texas Instruments is a highly versatile, low-jitter frequency synthesizer designed for various wireline and data communication applications. This device features an integrated voltage-controlled oscillator (VCO) and a phase-locked loop (PLL) that can be easily configured using control pins. It supports multiple output formats, including LVPECL, LVDS, and LVCMOS, making it suitable for a wide range of high-performance applications such as SONET, Ethernet, Fibre Channel, and HDTV.
Key Specifications
| Parameter | Minimum | Typical | Maximum | Unit |
|---|---|---|---|---|
| Input Frequency Range | 21.875 | - | 28.47 | MHz |
| VCO Frequency Range | 1.75 | - | 2.05 | GHz |
| Output Frequency Range | 43.75 | - | 683.264 | MHz |
| Supply Voltage | 3.0 | 3.3 | 3.6 | V |
| Operating Temperature | -40 | - | 85 | °C |
| Package Type | - | - | 32-pin QFN (RHB) | - |
| Random Jitter (RMS) | - | 0.509 | - | ps (10 kHz to 20 MHz) |
| Phase Noise at 5-MHz Offset | - | -146 | - | dBc/Hz |
Key Features
- Two universal output buffers configurable as LVPECL, LVDS, or LVCMOS.
- On-chip PLL with an on-chip VCO operating in the range of 1.75 GHz to 2.05 GHz.
- Divider programming using control pins for prescaler, feedback, and output dividers.
- Chip enable control pin and reset pin for device management.
- Low output skew of 20 ps on LVPECL outputs and output duty cycle corrected to 50% (± 5%).
- ESD protection exceeds 2 kV (HBM).
- Industrial temperature range: –40°C to +85°C.
- Small 32-pin QFN package with a size of 5-mm × 5-mm.
Applications
- Low-jitter clock driver for high-end datacom applications.
- SONET, Ethernet, Fibre Channel, and Serial ATA.
- HDTV and other high-performance video applications.
- Cost-effective high-frequency crystal oscillator replacement.
Q & A
- What is the input frequency range of the CDCM61002?
The input frequency range is from 21.875 MHz to 28.47 MHz.
- What are the possible output formats of the CDCM61002?
The outputs can be configured as LVPECL, LVDS, or LVCMOS.
- What is the operating temperature range of the CDCM61002?
The device operates from –40°C to +85°C.
- How is the PLL configured in the CDCM61002?
The PLL can be configured using control pins for prescaler, feedback, and output dividers.
- What is the typical random jitter performance of the CDCM61002?
The typical random jitter is 0.509 ps, RMS (from 10 kHz to 20 MHz).
- What is the phase noise at a 5-MHz offset for the CDCM61002?
The phase noise is typically at –146 dBc/Hz at a 5-MHz offset for a 625-MHz LVPECL output.
- What is the package type and size of the CDCM61002?
The device is packaged in a 32-pin QFN (RHB) package with a size of 5-mm × 5-mm.
- Does the CDCM61002 have ESD protection?
- What are some common applications of the CDCM61002?
- How is the output duty cycle of the CDCM61002 managed?
