Overview
The CDCM61001RHBR from Texas Instruments is a highly versatile, low-jitter frequency synthesizer designed to generate low-jitter clock outputs. This device is suitable for a variety of wireline and data communication applications, including SONET, Ethernet, Fibre Channel, and Storage Area Networks (SAN). It features an onboard Phase-Locked Loop (PLL) that can be easily configured using control pins, ensuring high-performance and low phase noise. The CDCM61001RHBR operates within an industrial temperature range of –40°C to +85°C and is packaged in a 32-pin, 5-mm × 5-mm QFN (RHB) package.
Key Specifications
| Parameter | Value | Unit |
|---|---|---|
| Input Frequency Range | 21.875 MHz to 28.47 MHz | MHz |
| On-Chip VCO Frequency Range | 1.75 GHz to 2.05 GHz | GHz |
| Output Frequency Range | 43.75 MHz to 683.28 MHz | MHz |
| Output Types | LVPECL, LVDS, LVCMOS | |
| Output Duty Cycle | 50% (± 5%) | % |
| Phase Noise at 5-MHz Offset | –146 dBc/Hz | dBc/Hz |
| Random Jitter (RMS) | < 1 ps (10 kHz to 20 MHz) | ps |
| Power Supply | 3.3 V | V |
| Package Type | 32-pin QFN (RHB) | |
| Package Size | 5-mm × 5-mm | mm |
| Temperature Range | –40°C to +85°C | °C |
| ESD Protection | Exceeds 2 kV (HBM) | kV |
Key Features
- One crystal/LVCMOS reference input supporting frequencies such as 24.8832 MHz, 25 MHz, and 26.5625 MHz.
- Pin-selectable output between LVPECL, LVDS, or LVCMOS, operating at 3.3 V.
- LVCMOS bypass output available to help with crystal loading.
- Output frequency selectable by /1, /2, /3, /4, /6, or /8 from the output divider.
- Supports common LVPECL/LVDS and LVCMOS output frequencies such as 62.5 MHz, 74.25 MHz, 75 MHz, etc..
- Divider programming using control pins for prescaler/feedback divider and output divider.
- Chip enable and device reset control pins available.
- High-performance PLL core with internal PLL loop bandwidth of 400 kHz.
- Low phase noise and random jitter performance, making it suitable for demanding applications.
Applications
- SONET and Ethernet clock generation.
- Fibre Channel and Storage Area Networks (SAN) clock generation.
- Serial ATA and HDTV applications.
- Low-jitter clock driver for high-end datacom applications.
- Cost-effective high-frequency crystal oscillator replacement).
Q & A
- What is the CDCM61001RHBR used for?
The CDCM61001RHBR is used as a low-jitter frequency synthesizer for various wireline and data communication applications, including SONET, Ethernet, Fibre Channel, and SAN.
- What are the supported input frequencies for the CDCM61001RHBR?
The device supports input frequencies ranging from 21.875 MHz to 28.47 MHz, including specific frequencies like 24.8832 MHz, 25 MHz, and 26.5625 MHz.
- What types of output signals can the CDCM61001RHBR generate?
The CDCM61001RHBR can generate output signals in LVPECL, LVDS, or LVCMOS formats, selectable via control pins.
- What is the output frequency range of the CDCM61001RHBR?
The output frequency range is from 43.75 MHz to 683.28 MHz.
- How is the output frequency of the CDCM61001RHBR configured?
The output frequency can be configured using control pins to select divide-by values of /1, /2, /3, /4, /6, or /8 from the output divider.
- What is the phase noise performance of the CDCM61001RHBR?
The phase noise is typically at –146 dBc/Hz at a 5-MHz offset.
- What is the random jitter performance of the CDCM61001RHBR?
The random jitter is typically less than 1 ps, RMS (from 10 kHz to 20 MHz).
- What is the power supply voltage for the CDCM61001RHBR?
The device operates on a 3.3-V core and I/O power supply.
- What is the package type and size of the CDCM61001RHBR?
The device is packaged in a 32-pin QFN (RHB) package with dimensions of 5-mm × 5-mm.
- What is the operating temperature range of the CDCM61001RHBR?
The device operates within an industrial temperature range of –40°C to +85°C.
