Overview
The CDCLVD1204, produced by Texas Instruments, is a 2:4 low additive jitter LVDS buffer designed for high-performance clock distribution. This device is capable of accepting two selectable clock inputs (LVDS, LVPECL, or LVCMOS) and distributing them to four pairs of differential LVDS clock outputs. It is optimized for driving 50-Ω transmission lines and features low additive jitter and low output skew, making it suitable for a variety of demanding applications.
Key Specifications
| Parameter | Value |
|---|---|
| Device Type | 2:4 Differential Buffer |
| Input Types | LVDS, LVPECL, LVCMOS |
| Output Type | LVDS (ANSI EIA/TIA-644A Standard Compatible) |
| Maximum Clock Frequency | Up to 800 MHz |
| Device Power Supply | 2.375 V to 2.625 V |
| Low Additive Jitter | < 300 fs RMS in 10-kHz to 20-MHz |
| Output Skew | 20 ps (Maximum) |
| Temperature Range | –40°C to 85°C |
| Package | 3 mm × 3 mm, 16-Pin VQFN (RGT) |
| ESD Protection | Exceeds 3 kV HBM, 1 kV CDM |
Key Features
- Low additive jitter: < 300 fs RMS in 10-kHz to 20-MHz frequency range.
- Low output skew: 20 ps (Maximum).
- Universal inputs: Accepts LVDS, LVPECL, and LVCMOS inputs.
- Selectable clock inputs: Through control pin (IN_SEL).
- Four LVDS outputs: Compliant with ANSI EIA/TIA-644A standard.
- LVDS reference voltage (VAC_REF): Available for capacitive coupled inputs.
- Fail-safe function: Prevents random oscillation of outputs in the absence of an input signal.
- Small package: 3 mm × 3 mm, 16-Pin VQFN (RGT).
Applications
- Telecommunications and Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General Purpose Clocking
Q & A
- What is the maximum clock frequency supported by the CDCLVD1204?
The CDCLVD1204 supports clock frequencies up to 800 MHz. - What types of input signals can the CDCLVD1204 accept?
The CDCLVD1204 can accept LVDS, LVPECL, and LVCMOS input signals. - How many LVDS output pairs does the CDCLVD1204 provide?
The CDCLVD1204 provides four pairs of differential LVDS clock outputs. - What is the typical additive jitter of the CDCLVD1204?
The typical additive jitter is less than 300 fs RMS in the 10-kHz to 20-MHz frequency range. - What is the output skew of the CDCLVD1204?
The maximum output skew is 20 ps. - What is the operating temperature range of the CDCLVD1204?
The operating temperature range is –40°C to 85°C. - What package type is the CDCLVD1204 available in?
The CDCLVD1204 is packaged in a 3 mm × 3 mm, 16-Pin VQFN (RGT). - Does the CDCLVD1204 have ESD protection?
Yes, the CDCLVD1204 exceeds 3 kV HBM and 1 kV CDM for ESD protection. - How does the IN_SEL pin function in the CDCLVD1204?
The IN_SEL pin selects the input which is routed to the outputs. If left open, it disables the outputs. - What is the purpose of the VAC_REF pin in the CDCLVD1204?
The VAC_REF pin provides the bias voltage for capacitive coupled inputs.
