Overview
The SPC560P40L1CEFAR is a 32-bit system-on-chip (SoC) automotive microcontroller from STMicroelectronics, designed for integrated automotive application controllers. It is part of the SPC560P family, which addresses chassis applications such as electrical hydraulic power steering (EHPS) and electric power steering (EPS), as well as airbag applications. This microcontroller is based on the Power Architecture technology and features a high-performance, cost-efficient host processor core that operates at speeds of up to 64 MHz, optimized for low power consumption.
Key Specifications
| Parameter | Specification |
|---|---|
| CPU Core | Up to 64 MHz, single issue, 32-bit CPU core complex (e200z0h) |
| Architecture | Compliant with Power Architecture embedded category |
| Memory | Up to 256 KB on-chip code flash memory with ECC and erase/program controller |
| Data Flash Memory | Additional 64 (4 × 16) KB on-chip data flash memory with ECC for EEPROM emulation |
| SRAM | Up to 20 KB on-chip SRAM with ECC |
| Interrupts and Events | 16-channel eDMA controller, 16 priority level controller, up to 25 external interrupts |
| Timers | PIT implements four 32-bit timers, 1 general purpose eTimer unit, 6 timers each with up/down capabilities |
| Communications Interfaces | 2 LINFlex channels, up to 3 DSPI channels, up to 2 FlexCAN interface (2.0B Active) |
| Analog-to-Digital Converter (ADC) | One 10-bit ADC with up to 16 input channels, conversion time < 1 μs including sampling time at full precision |
| GPIO | 37 on LQFP64, 64 on LQFP100, individually programmable as I/O or special function |
| Operating Temperature | Automotive grade, specific temperature range available in datasheet |
| Package | LQFP 64 10x10x1.4 mm |
| RoHS Compliance | Ecopack2 |
Key Features
- High-performance e200z0 core processor with Variable Length Encoding (VLE)
- Fail-safe protection, programmable watchdog timer, non-maskable interrupt, and fault collection unit
- Nexus Class 1 interface for debugging and development
- 16-channel eDMA controller and 16 priority level controller
- Up to 25 external interrupts and 120 interrupts routed via INTC
- Communications interfaces including LINFlex, DSPI, and FlexCAN
- One 10-bit analog-to-digital converter (ADC) with up to 16 input channels
- Programmable Cross Triggering Unit (CTU) and 4 analog watchdogs with interrupt capability
- On-chip CAN/UART bootstrap loader with Boot Assist Module (BAM)
- FlexPWM unit with 8 complementary or independent outputs and ADC synchronization signals
Applications
The SPC560P40L1CEFAR is specifically designed for automotive chassis and safety applications, including:
- Electrical Hydraulic Power Steering (EHPS)
- Electric Power Steering (EPS)
- Airbag applications
Q & A
- What is the CPU core frequency of the SPC560P40L1CEFAR?
Up to 64 MHz.
- What type of architecture does the SPC560P40L1CEFAR use?
Power Architecture embedded category.
- How much on-chip code flash memory does the SPC560P40L1CEFAR have?
Up to 256 KB with ECC and erase/program controller.
- What is the maximum number of external interrupts supported?
Up to 25 external interrupts.
- What communication interfaces are available on the SPC560P40L1CEFAR?
2 LINFlex channels, up to 3 DSPI channels, and up to 2 FlexCAN interface (2.0B Active).
- What is the resolution and conversion time of the ADC?
10-bit resolution, conversion time < 1 μs including sampling time at full precision.
- How many GPIO pins are available on the LQFP64 package?
37 GPIO pins.
- Is the SPC560P40L1CEFAR RoHS compliant?
- What is the operating temperature range for the SPC560P40L1CEFAR?
Specific temperature range available in the datasheet, generally suitable for automotive applications.
- What is the purpose of the Nexus Class 1 interface?
For debugging and development.
