Overview
The ADSP-21062CS-160 is a high-performance digital signal processor (DSP) from Analog Devices' SHARC® series. It is a 32-bit signal processing microcomputer designed to offer high levels of DSP performance. The ADSP-2106x SHARC processors build on the ADSP-21000 DSP core, integrating a dual-ported on-chip SRAM and various I/O peripherals supported by a dedicated I/O bus. Fabricated in a high-speed, low-power CMOS process, the ADSP-21062 operates at 40 MHz with a 25 ns instruction cycle time, achieving 120 MFLOPS peak performance.
Key Specifications
| Specification | Details |
|---|---|
| Processor Core | 40 MHz, 25 ns instruction rate SISD SHARC Core |
| Peak Performance | 120 MFLOPS |
| Instruction Set | Supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math |
| On-chip Memory | 2 Mbits of on-chip dual-ported SRAM |
| Host Processor Interface | Available for host processor connectivity |
| Link Ports | Six Link Ports for point-to-point connectivity and array multiprocessing |
| Synchronous Serial Ports | Two synchronous serial ports with independent transmit and receive functions |
| DMA Controller | 10 Channel DMA controller |
| Power Supply | Operates at 5V |
Key Features
- High Performance DSP Core: The ADSP-21062 features a high-performance floating-point DSP core with a 25 ns instruction cycle time and 120 MFLOPS peak performance.
- Dual-Ported On-Chip SRAM: The processor includes 2 Mbits of on-chip dual-ported SRAM, allowing for single-cycle, independent accesses by the core processor and I/O processor or DMA controller.
- Integrated I/O Peripherals: Includes a host processor interface, DMA controller, two synchronous serial ports, and six link ports for glueless DSP multiprocessing.
- Code Compatibility: Code compatible with all SHARC processors, ensuring ease of migration and development.
- Instruction Cache: On-chip instruction cache allows the processor to execute every instruction in a single cycle.
Applications
The ADSP-21062CS-160 is optimized for high-performance DSP applications, including but not limited to:
- Audio Processing: High-quality audio processing, such as audio compression, filtering, and effects.
- Image Processing: Image processing tasks like image compression, filtering, and enhancement.
- Telecommunications: Telecommunication systems requiring high-speed signal processing, such as modems and baseband processing.
- Medical Imaging: Medical imaging applications, including MRI, CT scans, and ultrasound processing.
- Industrial Control: Industrial control systems that require advanced signal processing capabilities.
Q & A
- What is the clock speed of the ADSP-21062CS-160?
The ADSP-21062CS-160 operates at a clock speed of 40 MHz with a 25 ns instruction cycle time.
- What is the peak performance of the ADSP-21062CS-160?
The peak performance of the ADSP-21062CS-160 is 120 MFLOPS.
- How much on-chip SRAM does the ADSP-21062CS-160 have?
The ADSP-21062CS-160 has 2 Mbits of on-chip dual-ported SRAM.
- What types of math does the ADSP-21062CS-160 support?
The ADSP-21062CS-160 supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math.
- Does the ADSP-21062CS-160 have any serial ports?
Yes, the ADSP-21062CS-160 has two synchronous serial ports with independent transmit and receive functions.
- How many link ports does the ADSP-21062CS-160 have?
The ADSP-21062CS-160 has six link ports for point-to-point connectivity and array multiprocessing.
- Is the ADSP-21062CS-160 code compatible with other SHARC processors?
Yes, the ADSP-21062CS-160 is code compatible with all SHARC processors.
- What is the power supply voltage for the ADSP-21062CS-160?
The ADSP-21062CS-160 operates at 5V.
- Does the ADSP-21062CS-160 have a DMA controller?
Yes, the ADSP-21062CS-160 has a 10 Channel DMA controller.
- What kind of instruction cache does the ADSP-21062CS-160 have?
The ADSP-21062CS-160 has an on-chip instruction cache that allows the processor to execute every instruction in a single cycle.
