Overview
The ADSP-21060LKSZ-160, produced by Analog Devices Inc., is a member of the SHARC (Super Harvard Architecture Computer) family of digital signal processors (DSPs). This 32-bit signal processing microcomputer is designed to offer high levels of DSP performance, making it suitable for a wide range of high-performance signal processing applications. The ADSP-21060LKSZ-160 builds on the ADSP-21000 DSP core, integrating a complete system-on-a-chip with advanced features such as dual-ported on-chip SRAM, integrated I/O peripherals, and a dedicated I/O bus.
Key Specifications
| Specification | Details |
|---|---|
| Processor Core | 40MHz (25ns instruction rate) SISD SHARC Core |
| Peak Performance | 120 MFLOPS |
| Instruction Set | Code compatible with all SHARC processors |
| Math Support | IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math |
| On-Chip Memory | 4Mbits of on-chip dual-ported SRAM |
| Link Ports | Six Link Ports for point to point connectivity and array multiprocessing |
| Serial Ports | Two synchronous serial ports with independent transmit and receive functions |
| DMA Controller | 10 Channel DMA controller |
| Host Processor Interface | Host Processor Interface |
| Package | 225-Ball PBGA (23mm x 20mm) or 240-Lead CQFP, Heat Slug Down |
| Voltage | 3.3V |
Key Features
- High Performance DSP Core: The ADSP-21060LKSZ-160 features a 40MHz SISD SHARC Core with a 25ns instruction cycle time, operating at 40 MIPS.
- Integrated Memory: It includes 4Mbits of on-chip dual-ported SRAM, allowing for efficient single-cycle accesses by the core processor and I/O processor or DMA controller.
- Scalable Multiprocessing: The processor supports glueless connection for scalable DSP multiprocessing through six Link Ports and parallel bus connectivity.
- Advanced I/O Peripherals: It includes two synchronous serial ports, a 10 Channel DMA controller, and a host processor interface.
- Mathematical Capabilities: Supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math.
- Low Power CMOS Process: Fabricated in a high speed, low power CMOS process to optimize performance and power consumption.
Applications
The ADSP-21060LKSZ-160 is designed for high-performance signal processing applications, including but not limited to:
- Aerospace and Defense Systems
- Medical Imaging and Diagnostic Equipment
- Industrial Automation and Control Systems
- Telecommunications and Networking Equipment
- Audio and Video Processing Systems
Q & A
- What is the peak performance of the ADSP-21060LKSZ-160?
The peak performance of the ADSP-21060LKSZ-160 is 120 MFLOPS.
- What type of math does the ADSP-21060LKSZ-160 support?
The ADSP-21060LKSZ-160 supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math.
- How much on-chip memory does the ADSP-21060LKSZ-160 have?
The ADSP-21060LKSZ-160 has 4Mbits of on-chip dual-ported SRAM.
- What is the instruction cycle time of the ADSP-21060LKSZ-160?
The instruction cycle time is 25ns, with an operating frequency of 40MHz.
- Does the ADSP-21060LKSZ-160 support multiprocessing?
Yes, it supports glueless connection for scalable DSP multiprocessing through six Link Ports and parallel bus connectivity.
- What are the key I/O peripherals of the ADSP-21060LKSZ-160?
The key I/O peripherals include two synchronous serial ports, a 10 Channel DMA controller, and a host processor interface.
- What is the voltage requirement of the ADSP-21060LKSZ-160?
The ADSP-21060LKSZ-160 operates at 3.3V.
- What are the typical applications of the ADSP-21060LKSZ-160?
Typical applications include aerospace and defense systems, medical imaging, industrial automation, telecommunications, and audio/video processing.
- Is the ADSP-21060LKSZ-160 code compatible with other SHARC processors?
Yes, the ADSP-21060LKSZ-160 is code compatible with all SHARC processors.
- What is the package type of the ADSP-21060LKSZ-160?
The ADSP-21060LKSZ-160 is available in 225-Ball PBGA (23mm x 20mm) or 240-Lead CQFP, Heat Slug Down packages.
