Overview
The ADSP-21062KS-160 is a high-performance digital signal processor (DSP) from Analog Devices Inc., part of the SHARC (Super Harvard Architecture Computer) family. This 32-bit signal processing microcomputer is designed to offer advanced capabilities and high levels of performance, making it suitable for a wide range of signal processing applications. The ADSP-21062KS-160 builds on the ADSP-21000 DSP core, integrating a complete system-on-a-chip with dual-ported on-chip SRAM, host processor interface, DMA controller, serial ports, and link ports for scalable DSP multiprocessing.
Key Specifications
| Specification | Value |
|---|---|
| Instruction Rate | 40 MHz (25 ns instruction cycle time) |
| Peak Performance | 120 MFLOPS |
| On-chip SRAM | 2 Mbits (dual-ported) |
| Operating Voltage | 5 V |
| Package Type | 240-pin MQFP-PQ4 surface mount package |
| Serial Ports | Two 40 Mbps synchronous serial ports with independent transmit and receive functions |
| Link Ports | Six link ports for point-to-point connectivity and array multiprocessing |
| DMA Controller | 10-channel DMA controller |
| Math Support | IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math |
Key Features
- High-performance 32-bit SHARC DSP core with 40 MIPS operation and 120 MFLOPS peak performance.
- Dual-ported on-chip SRAM, allowing single-cycle, independent accesses by the core processor and I/O processor or DMA controller.
- Host processor interface for seamless integration with other systems.
- Six link ports for point-to-point connectivity and array multiprocessing, enabling glueless DSP multiprocessing.
- Two synchronous serial ports with independent transmit and receive functions.
- 10-channel DMA controller for efficient data transfer.
- Support for IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math.
- Fabricated in a high-speed, low-power CMOS process.
Applications
- Aerospace and defense systems requiring high-performance signal processing.
- Medical imaging and diagnostic equipment.
- Industrial control and automation systems.
- Telecommunications and wireless communication systems.
- Audio and video processing applications.
- Radar and sonar systems.
Q & A
- What is the instruction rate of the ADSP-21062KS-160?
The ADSP-21062KS-160 operates at an instruction rate of 40 MHz with a 25 ns instruction cycle time.
- How much on-chip SRAM does the ADSP-21062KS-160 have?
The ADSP-21062KS-160 has 2 Mbits of dual-ported on-chip SRAM.
- What types of math does the ADSP-21062KS-160 support?
The ADSP-21062KS-160 supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math.
- What is the package type of the ADSP-21062KS-160?
The ADSP-21062KS-160 is packaged in a 240-pin MQFP-PQ4 surface mount package.
- Does the ADSP-21062KS-160 support multiprocessing?
- What is the operating voltage of the ADSP-21062KS-160?
The ADSP-21062KS-160 operates at 5 V.
- How many serial ports does the ADSP-21062KS-160 have?
The ADSP-21062KS-160 has two 40 Mbps synchronous serial ports with independent transmit and receive functions.
- What is the role of the DMA controller in the ADSP-21062KS-160?
The 10-channel DMA controller in the ADSP-21062KS-160 manages efficient data transfer between different parts of the system.
- Is the ADSP-21062KS-160 code compatible with other SHARC processors?
- What are some typical applications of the ADSP-21062KS-160?
The ADSP-21062KS-160 is used in various applications including aerospace and defense, medical imaging, industrial control, telecommunications, and audio/video processing.
