Overview
The ADSP-21061LKBZ-160, produced by Analog Devices Inc., is a member of the powerful SHARC (Super Harvard Architecture Computer) family of floating-point processors. This 32-bit processor is optimized for high-performance digital signal processing (DSP) applications. It combines the ADSP-21000 DSP core with a dual-ported on-chip SRAM and an I/O processor, forming a complete system-on-a-chip. Fabricated in a high-speed, low-power CMOS process, the ADSP-21061 operates at 50 MHz with a 20 ns instruction cycle time, achieving 150 MFLOPS peak performance.
Key Specifications
| Parameter | Value |
|---|---|
| Processor Core | SHARC (Super Harvard Architecture Computer) |
| Instruction Rate | 50 MHz (20 ns instruction cycle time) |
| Peak Performance | 150 MFLOPS |
| Math Support | IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math |
| On-chip Memory | 1 Mbit dual-ported SRAM |
| Interface | Two synchronous serial ports, Host Processor Interface, 6 Channel DMA controller |
| Package Type | 225-Ball PBGA (Plastic Ball Grid Array) |
| Max Operating Temperature | 85 °C |
| Max Supply Voltage | 3.45 V (for ADSP-21061L models) |
Key Features
- High-Performance DSP Core: Optimized for high-performance DSP applications with a 50 MHz clock rate and 150 MFLOPS peak performance.
- Integrated System Features: Includes 1 Mbit of on-chip dual-ported SRAM, host processor interface, DMA controller, and two synchronous serial ports.
- Code Compatibility: Code compatible with all SHARC processors, facilitating easy migration and development.
- Glueless Multiprocessing: Supports scalable DSP multiprocessing without the need for additional glue logic.
- Low Power CMOS Process: Fabricated in a high-speed, low-power CMOS process to minimize power consumption.
Applications
The ADSP-21061LKBZ-160 is suitable for a wide range of high-performance DSP applications, including:
- Audio Processing: Real-time audio processing, audio effects, and audio compression.
- Image Processing: Image enhancement, image compression, and video processing.
- Telecommunications: Modem design, echo cancellation, and voice compression.
- Medical Imaging: Ultrasound, MRI, and CT scan processing.
- Industrial Control: Real-time control systems and signal processing in industrial automation.
Q & A
- What is the ADSP-21061LKBZ-160 processor's clock speed?
The ADSP-21061LKBZ-160 operates at a clock speed of 50 MHz with a 20 ns instruction cycle time.
- What is the peak performance of the ADSP-21061LKBZ-160?
The peak performance is 150 MFLOPS.
- What type of math does the ADSP-21061LKBZ-160 support?
It supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math.
- How much on-chip memory does the ADSP-21061LKBZ-160 have?
It has 1 Mbit of dual-ported SRAM.
- What interfaces does the ADSP-21061LKBZ-160 provide?
It includes two synchronous serial ports, a host processor interface, and a 6 Channel DMA controller.
- What is the maximum operating temperature of the ADSP-21061LKBZ-160?
The maximum operating temperature is 85 °C.
- What is the maximum supply voltage for the ADSP-21061L models?
The maximum supply voltage is 3.45 V.
- Is the ADSP-21061LKBZ-160 code compatible with other SHARC processors?
Yes, it is code compatible with all SHARC processors.
- Does the ADSP-21061LKBZ-160 support glueless DSP multiprocessing?
Yes, it supports scalable DSP multiprocessing without the need for additional glue logic.
- In what process is the ADSP-21061LKBZ-160 fabricated?
It is fabricated in a high-speed, low-power CMOS process.
