Overview
The ADSP-21065LCS-240, produced by Analog Devices Inc., is a general-purpose, programmable 32-bit Digital Signal Processor (DSP) that belongs to the SHARC family. This processor is optimized for cost-sensitive applications while maintaining high performance and memory integration. It supports both fixed-point and floating-point arithmetic, making it versatile for a wide range of consumer, communications, automotive, industrial, and computer applications. The ADSP-21065L is code compatible with other SHARC DSPs, ensuring immediate access to software and hardware development tools from Analog Devices and third-party providers.
Key Specifications
| Parameter | Specification |
|---|---|
| Instruction Rate | 60 MHz / 66 MHz |
| Performance | 198 MFLOPS (32-bit floating-point) |
| On-Chip Memory | 16K 32-bit Dual-ported on-chip memory (544 KBits configurable) |
| External Address Space | 64M x 32-bit word |
| Memory Interface | Glueless SDRAM interface |
| Serial Ports | 2 serial transmit/receive ports supporting 32-channel TDM |
| Timers | Two timers with event capture and PWM options |
| I/O Pins | 12 programmable I/O pins |
| DMA Channels | 10 DMA channels |
| Operating Voltage | 3.3V |
| Operating Temperature | –40°C to +100°C |
| Package | MQFP-208 |
Key Features
- Flexible Instruction Set: The 48-bit instruction word allows for a variety of parallel operations, enabling concise programming. For example, the ADSP-21065L can conditionally execute a multiply, an add, a subtract, and a branch all in a single instruction.
- Dual-Ported On-Chip Memory: The processor contains 544 Kbits of on-chip SRAM, organized into two banks, allowing single-cycle, independent accesses by the core processor and I/O processor or DMA controller.
- Glueless Multiprocessing: Supports multiprocessing with up to two ADSP-21065Ls.
- Integrated Peripherals: Includes a host processor interface, DMA controller, SDRAM controller, and two timers with event capture and PWM options.
- Program Booting: Internal memory can be booted from an 8-bit EPROM, a host processor, or external memory.
- Aerospace and Defense Compliance: Meets AQEC standards with extended temperature range and controlled manufacturing baseline.
Applications
The ADSP-21065L is suitable for a broad range of applications, including:
- Consumer electronics
- Communications systems
- Automotive systems
- Industrial control systems
- Computer systems
- Aerospace and defense applications
Q & A
- What is the instruction rate of the ADSP-21065L?
The ADSP-21065L has instruction rates of 60 MHz and 66 MHz.
- What is the performance of the ADSP-21065L in terms of MFLOPS?
The ADSP-21065L achieves 198 MFLOPS for 32-bit floating-point operations.
- How much on-chip memory does the ADSP-21065L have?
The ADSP-21065L has 16K 32-bit dual-ported on-chip memory, configurable to 544 KBits.
- What types of serial ports does the ADSP-21065L support?
The ADSP-21065L supports two serial transmit/receive ports with up to 32-channel TDM.
- Does the ADSP-21065L support multiprocessing?
Yes, the ADSP-21065L supports glueless multiprocessing with up to two ADSP-21065Ls.
- What is the operating voltage of the ADSP-21065L?
The operating voltage of the ADSP-21065L is 3.3V.
- What is the operating temperature range of the ADSP-21065L?
The operating temperature range is –40°C to +100°C.
- What package types are available for the ADSP-21065L?
The ADSP-21065L is available in MQFP-208 and CSPBGA packages.
- Is the ADSP-21065L compliant with aerospace and defense standards?
Yes, the ADSP-21065L meets AQEC standards and has an extended temperature range and controlled manufacturing baseline.
- How can the internal memory of the ADSP-21065L be booted?
The internal memory can be booted from an 8-bit EPROM, a host processor, or external memory.
