Overview
The ADSP-21061KSZ-160, produced by Analog Devices Inc., is a member of the powerful SHARC (Super Harvard Architecture Computer) family of floating-point processors. This 32-bit processor is optimized for high-performance digital signal processing (DSP) applications. It combines the ADSP-21000 DSP core with a dual-ported on-chip SRAM and an I/O processor, along with a dedicated I/O bus, to form a complete system-on-a-chip. Fabricated in a high-speed, low-power CMOS process, the ADSP-21061 operates at 50 MHz with a 20 ns instruction cycle time, achieving 50 MIPS and 150 MFLOPS peak performance.
Key Specifications
| Specification | Value |
|---|---|
| Processor Speed | 50 MHz |
| Instruction Cycle Time | 20 ns |
| MIPS | 50 MIPS |
| Peak Performance | 150 MFLOPS |
| On-chip SRAM | 1 Mbit dual-ported SRAM |
| Instruction Set | 48-bit instruction word, supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math |
| I/O Peripherals | Host processor interface, DMA controller, two synchronous serial ports, parallel bus connectivity |
| Package Type | 240-lead thermally enhanced MQFP |
| Operating Voltage | 5 V (ADSP-21061), 3.3 V (ADSP-21061L) |
Key Features
- High-performance 32-bit DSP core with integrated on-chip system features.
- Supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math.
- 1 Mbit of on-chip dual-ported SRAM for efficient data and instruction access.
- Glueless connection for scalable DSP multiprocessing.
- Two synchronous serial ports with independent transmit and receive functions.
- 6-channel DMA controller for efficient data transfer.
- Host processor interface and multiprocessor interface for system integration.
- JTAG test access port for debugging and testing.
- Data address generators with hardware circular buffers for efficient programming of delay lines and other data structures.
Applications
The ADSP-21061KSZ-160 is suitable for a wide range of high-performance DSP applications, including:
- Audio and video processing.
- Medical imaging and diagnostics.
- Radar and sonar systems.
- Industrial control and automation.
- Telecommunications and wireless communication systems.
Q & A
- What is the operating frequency of the ADSP-21061KSZ-160?
The ADSP-21061KSZ-160 operates at 50 MHz.
- What is the instruction cycle time of the ADSP-21061KSZ-160?
The instruction cycle time is 20 ns.
- What is the peak performance of the ADSP-21061KSZ-160?
The peak performance is 150 MFLOPS.
- How much on-chip SRAM does the ADSP-21061KSZ-160 have?
The ADSP-21061KSZ-160 has 1 Mbit of dual-ported on-chip SRAM.
- What types of math does the ADSP-21061KSZ-160 support?
The ADSP-21061KSZ-160 supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math.
- Does the ADSP-21061KSZ-160 support multiprocessing?
Yes, it supports glueless DSP multiprocessing with parallel bus connectivity.
- What kind of I/O peripherals does the ADSP-21061KSZ-160 have?
The ADSP-21061KSZ-160 includes a host processor interface, DMA controller, two synchronous serial ports, and parallel bus connectivity.
- What is the package type of the ADSP-21061KSZ-160?
The package type is a 240-lead thermally enhanced MQFP.
- What are the operating voltages for the ADSP-21061 and ADSP-21061L?
The ADSP-21061 operates at 5 V, while the ADSP-21061L operates at 3.3 V.
- Does the ADSP-21061KSZ-160 have any special features for data addressing?
Yes, it includes data address generators with hardware circular buffers for efficient programming of delay lines and other data structures.
