Overview
The AD9628BCPZRL7-125, produced by Analog Devices Inc., is a monolithic, dual-channel, 12-bit analog-to-digital converter (ADC) operating at a maximum sample rate of 125 MSPS. It features a high-performance sample-and-hold circuit and an on-chip voltage reference. The ADC uses a multistage differential pipeline architecture with output error correction logic to ensure 12-bit accuracy and guarantee no missing codes over the full operating temperature range of -40°C to +85°C. The device operates from a single 1.8 V analog power supply and has a separate digital output driver supply that supports 1.8 V CMOS or LVDS logic families.
Key Specifications
| Parameter | Min | Typ | Max | Unit |
|---|---|---|---|---|
| Resolution | 12 | 12 | 12 | Bits |
| Accuracy (No Missing Codes) | Guaranteed | Guaranteed | Guaranteed | |
| Offset Error | -1.0 | -0.3 | +0.4 | LSB |
| SNR | 71.2 | dBFS at 70 MHz | ||
| SFDR | 93 | dBc at 70 MHz | ||
| Power Consumption per Channel | 101 | mW at 125 MSPS | ||
| Analog Input Bandwidth | 650 | MHz | ||
| Input Frequency Range | Up to 200 | MHz | ||
| Differential Analog Input | 2 | V p-p | ||
| DNL | ±0.25 | LSB | ||
| Operating Supply Voltage | 1.8 | 1.8 | V | |
| Operating Temperature Range | -40 | +85 | °C |
Key Features
- 1.8 V analog supply operation and separate 1.8 V digital output driver supply for CMOS or LVDS logic families.
- High-performance sample-and-hold circuit for input frequencies up to 200 MHz.
- On-chip voltage reference and multistage differential pipeline architecture with output error correction logic.
- Programmable clock and data alignment, and programmable digital test pattern generation including deterministic, pseudorandom, and custom user-defined patterns.
- Differential clock input and optional duty cycle stabilizer (DCS) for compensating clock duty cycle variations.
- Output data presented in offset binary, Gray code, or twos complement format, with data output clock (DCO) for each ADC channel.
- Support for 1.8 V CMOS or LVDS output logic levels, with the option to multiplex output data onto a single output bus.
- Standard serial port interface (SPI) for setup and control, including features like data output formatting, internal clock divider, power-down, and timing adjustments.
Applications
- Communications systems
- Diversity radio systems
- Multimode digital receivers (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA).
Q & A
- What is the maximum sample rate of the AD9628BCPZRL7-125?
The maximum sample rate of the AD9628BCPZRL7-125 is 125 MSPS.
- What is the resolution of the AD9628BCPZRL7-125?
The resolution of the AD9628BCPZRL7-125 is 12 bits.
- What is the operating supply voltage of the AD9628BCPZRL7-125?
The operating supply voltage of the AD9628BCPZRL7-125 is 1.8 V for both analog and digital supplies.
- What is the operating temperature range of the AD9628BCPZRL7-125?
The operating temperature range of the AD9628BCPZRL7-125 is -40°C to +85°C.
- What types of output logic levels are supported by the AD9628BCPZRL7-125?
The AD9628BCPZRL7-125 supports 1.8 V CMOS or LVDS output logic levels.
- What is the bandwidth of the analog input of the AD9628BCPZRL7-125?
The bandwidth of the analog input of the AD9628BCPZRL7-125 is 650 MHz.
- Does the AD9628BCPZRL7-125 have an on-chip voltage reference?
Yes, the AD9628BCPZRL7-125 has an on-chip voltage reference.
- What types of digital test patterns can be generated by the AD9628BCPZRL7-125?
The AD9628BCPZRL7-125 can generate deterministic, pseudorandom, and custom user-defined digital test patterns.
- What is the power consumption per channel of the AD9628BCPZRL7-125 at 125 MSPS?
The power consumption per channel of the AD9628BCPZRL7-125 at 125 MSPS is 101 mW.
- Is the AD9628BCPZRL7-125 RoHS compliant?
Yes, the AD9628BCPZRL7-125 is RoHS compliant.
