Overview
The AD9628BCPZ-125 is a high-performance, dual-channel analog-to-digital converter (ADC) produced by Analog Devices Inc. This monolithic device operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V CMOS or LVDS logic families. The AD9628 is designed with a multistage differential pipeline architecture and includes an on-chip voltage reference and a patented sample-and-hold circuit, ensuring excellent performance for input frequencies up to 200 MHz. It is packaged in a 64-lead RoHS-compliant Lead Frame Chip Scale Package (LFCSP) and is specified over the industrial temperature range of −40°C to +85°C.
Key Specifications
| Parameter | Min | Typ | Max | Unit |
|---|---|---|---|---|
| Resolution | 12 | 12 | 12 | Bits |
| Accuracy (No Missing Codes) | Guaranteed | Guaranteed | Guaranteed | |
| Offset Error | -1.0 | -0.3 | +0.4 | LSB |
| Sample Rate | 105 MSPS / 125 MSPS | MSPS | ||
| Analog Supply Voltage | 1.8 V | V | ||
| Digital Output Logic Levels | 1.8 V CMOS or LVDS | |||
| Power Consumption (per channel) | 101 mW | mW | ||
| Analog Input Bandwidth | 650 MHz | MHz | ||
| SNR at 70 MHz | 71.2 dBFS | dBFS | ||
| SFDR at 70 MHz | 93 dBc | dBc |
Key Features
- Operates from a single 1.8 V analog power supply with separate digital output driver supply for 1.8 V CMOS or LVDS logic families.
- High-performance sample-and-hold circuit and on-chip voltage reference.
- Multistage differential pipeline architecture with output error correction logic to ensure 12-bit accuracy and no missing codes over the full operating temperature range.
- Differential analog input with 650 MHz bandwidth and IF sampling frequencies up to 200 MHz.
- Low power consumption: 101 mW per channel at 125 MSPS.
- Programmable clock and data alignment, and programmable digital test pattern generation via SPI interface.
- Differential clock input with optional duty cycle stabilizer (DCS) to compensate for clock duty cycle variations.
- Supports offset binary, Gray code, or twos complement output data formats.
- Data output clock (DCO) for each ADC channel to ensure proper latch timing with receiving logic.
Applications
- Communications systems
- Diversity radio systems
- Multimode digital receivers (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA).
Q & A
- What is the resolution of the AD9628BCPZ-125 ADC?
The AD9628BCPZ-125 has a resolution of 12 bits.
- What are the supported digital output logic levels for the AD9628BCPZ-125?
The AD9628BCPZ-125 supports 1.8 V CMOS or LVDS output logic levels.
- What is the maximum sample rate of the AD9628BCPZ-125?
The maximum sample rate of the AD9628BCPZ-125 is 125 MSPS, with another variant at 105 MSPS.
- What is the power consumption per channel at 125 MSPS?
The power consumption per channel at 125 MSPS is 101 mW.
- What is the bandwidth of the analog input?
The analog input bandwidth is 650 MHz.
- Does the AD9628BCPZ-125 support programmable digital test patterns?
Yes, the AD9628BCPZ-125 supports programmable digital test patterns via the SPI interface, including built-in deterministic and pseudorandom patterns, as well as custom user-defined patterns.
- What is the purpose of the duty cycle stabilizer (DCS) in the AD9628BCPZ-125?
The duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle to maintain excellent overall ADC performance.
- What are the supported output data formats for the AD9628BCPZ-125?
The AD9628BCPZ-125 supports offset binary, Gray code, or twos complement output data formats.
- Is the AD9628BCPZ-125 RoHS-compliant?
Yes, the AD9628BCPZ-125 is packaged in a 64-lead RoHS-compliant LFCSP.
- What is the operating temperature range of the AD9628BCPZ-125?
The operating temperature range is from −40°C to +85°C.
