Overview
The AD9648BCPZ-125, produced by Analog Devices Inc., is a high-performance, dual-channel, 14-bit analog-to-digital converter (ADC). It operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V CMOS or LVDS logic families. This ADC is designed for low power consumption, ease of use, and high accuracy, making it suitable for a variety of applications in communications and other high-speed data acquisition systems.
Key Specifications
| Parameter | Value | Conditions |
|---|---|---|
| Resolution | 14 bits | |
| Sample Rate | 125 MSPS | |
| Analog Supply Voltage | 1.8 V | |
| Digital Output Logic | 1.8 V CMOS or LVDS | |
| Signal-to-Noise Ratio (SNR) | 74.5 dBFS at 70 MHz | VIN = −1.0 dBFS differential input |
| Spurious-Free Dynamic Range (SFDR) | 91 dBc at 70 MHz | VIN = −1.0 dBFS differential input |
| Power Consumption | 106 mW/channel at 125 MSPS | |
| Analog Input Bandwidth | 650 MHz | |
| Operating Temperature Range | −40°C to +85°C | |
| Package Type | 64-lead RoHS compliant LFCSP |
Key Features
- High performance sample-and-hold circuit with excellent performance for input frequencies up to 200 MHz.
- Programmable clock and data alignment, and programmable digital test pattern generation.
- Differential analog input with 650 MHz bandwidth.
- Support for IF sampling frequencies up to 200 MHz.
- Optional duty cycle stabilizer (DCS) to compensate for wide variations in the clock duty cycle.
- Digital output data presented in offset binary, Gray code, or twos complement format.
- Data output clock (DCO) provided for each ADC channel to ensure proper latch timing with receiving logic.
- Output logic levels of 1.8 V CMOS or LVDS supported.
- Output data can be multiplexed onto a single output bus.
- Standard serial port interface (SPI) for setup and control.
Applications
- Communications systems.
- Diversity radio systems.
- Multimode digital receivers (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA).
Q & A
- What is the resolution of the AD9648BCPZ-125 ADC?
The AD9648BCPZ-125 has a resolution of 14 bits.
- What is the maximum sample rate of the AD9648BCPZ-125?
The maximum sample rate is 125 MSPS.
- What are the supported digital output logic levels?
The AD9648BCPZ-125 supports 1.8 V CMOS or LVDS logic levels.
- What is the power consumption per channel at 125 MSPS?
The power consumption per channel is 106 mW at 125 MSPS.
- What is the operating temperature range of the AD9648BCPZ-125?
The operating temperature range is −40°C to +85°C.
- What type of package does the AD9648BCPZ-125 come in?
The AD9648BCPZ-125 is packaged in a 64-lead RoHS compliant LFCSP.
- Does the AD9648BCPZ-125 support programmable digital test patterns?
Yes, it supports programmable digital test pattern generation, including built-in deterministic and pseudorandom patterns, as well as custom user-defined test patterns via the SPI interface.
- What is the bandwidth of the analog input?
The analog input bandwidth is 650 MHz.
- Can the output data be multiplexed onto a single output bus?
Yes, the output data can be multiplexed onto a single output bus.
- What interface is used for setup and control of the AD9648BCPZ-125?
A standard serial port interface (SPI) is used for setup and control.
