Overview
The AD9648BCPZRL7-125 is a high-performance, dual-channel, 14-bit analog-to-digital converter (ADC) produced by Analog Devices Inc. This monolithic ADC operates from a single 1.8 V analog power supply and features a separate digital output driver supply to support 1.8 V CMOS or LVDS logic families. It is designed for low power consumption, ease of use, and high accuracy, making it suitable for a variety of applications in communications and other high-speed data acquisition systems.
Key Specifications
| Parameter | Min | Typ | Max | Unit |
|---|---|---|---|---|
| Resolution | 14 bits | |||
| Sampling Rate | 105 | 125 | MSPS | |
| Analog Supply Voltage (AVDD) | 1.7 | 1.8 | 1.9 | V |
| Digital Output Driver Supply (DRVDD) | 1.7 | 1.8 | 1.9 | V |
| Power Consumption (per channel at 125 MSPS) | 106 | mW | ||
| Signal-to-Noise Ratio (SNR) at 70 MHz | 74.5 | dBFS | ||
| Spurious Free Dynamic Range (SFDR) at 70 MHz | 91 | dBc | ||
| Analog Input Bandwidth | 650 | MHz | ||
| Input Common-Mode Voltage | 0.5 | 0.9 | 1.3 | V |
| Operating Temperature Range | -40 | 85 | °C | |
| Package Type | 64-lead RoHS compliant LFCSP | |||
Key Features
- Operates from a single 1.8 V analog power supply with separate digital output driver supply for 1.8 V CMOS or LVDS logic families.
- High performance sample-and-hold circuit for input frequencies up to 200 MHz.
- Programmable clock and data alignment, and programmable digital test pattern generation.
- Digital output data presented in offset binary, Gray code, or twos complement format.
- Optional duty cycle stabilizer (DCS) to compensate for wide variations in the clock duty cycle.
- Standard serial port interface (SPI) for setup and control.
- Low power consumption: 106 mW per channel at 125 MSPS.
- Packaged in a 64-lead RoHS compliant LFCSP, pin compatible with other ADCs from Analog Devices.
Applications
- Communications systems.
- Diversity radio systems.
- Multimode digital receivers for GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA.
Q & A
- What is the resolution of the AD9648BCPZRL7-125 ADC?
The AD9648BCPZRL7-125 has a resolution of 14 bits. - What are the sampling rates supported by the AD9648BCPZRL7-125?
The AD9648BCPZRL7-125 supports sampling rates of 105 MSPS and 125 MSPS. - What is the analog supply voltage for the AD9648BCPZRL7-125?
The analog supply voltage is 1.8 V. - What are the supported digital output logic levels for the AD9648BCPZRL7-125?
The AD9648BCPZRL7-125 supports 1.8 V CMOS or LVDS logic levels. - What is the power consumption per channel at 125 MSPS for the AD9648BCPZRL7-125?
The power consumption per channel at 125 MSPS is 106 mW. - What is the signal-to-noise ratio (SNR) of the AD9648BCPZRL7-125 at 70 MHz?
The SNR at 70 MHz is 74.5 dBFS. - What is the spurious free dynamic range (SFDR) of the AD9648BCPZRL7-125 at 70 MHz?
The SFDR at 70 MHz is 91 dBc. - What is the bandwidth of the analog input for the AD9648BCPZRL7-125?
The analog input bandwidth is 650 MHz. - What is the operating temperature range for the AD9648BCPZRL7-125?
The operating temperature range is -40°C to +85°C. - What package type is the AD9648BCPZRL7-125 available in?
The AD9648BCPZRL7-125 is available in a 64-lead RoHS compliant LFCSP.
