Overview
The AD9627BCPZ-125 is a high-performance, dual, 12-bit analog-to-digital converter (ADC) produced by Analog Devices Inc. This component is designed to support communications applications where low cost, small size, and versatility are essential. The AD9627 features a multistage, differential pipelined architecture with integrated output error correction logic, ensuring high accuracy and reliability. Each ADC includes wide bandwidth differential sample-and-hold analog input amplifiers that support various user-selectable input ranges. An integrated voltage reference simplifies design considerations, and a duty cycle stabilizer compensates for variations in the ADC clock duty cycle, maintaining excellent performance.
Key Specifications
| Parameter | Min | Typ | Max | Unit |
|---|---|---|---|---|
| Resolution | 12 | 12 | 12 | Bits |
| Sample Rate | 80 | 125 | 125 | MSPS |
| Offset Error | ±0.3 | ±0.6 | ±0.6 | % FSR |
| Gain Error | −0.7 | −2.7 | −3.9 | % FSR |
| Differential Nonlinearity (DNL) | ±0.4 | ±0.9 | ±0.9 | LSB |
| Integral Nonlinearity (INL) | ±0.9 | ±1.3 | ±1.3 | LSB |
| Input Resistance | 26 | kΩ | ||
| Input Capacitance | 5 | pF | ||
| Power Dissipation | 750 | mW | ||
| Operating Supply Voltage | 1.8 | 1.8 | V | |
| Output Type | CMOS, LVDS |
Key Features
- Integrated dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS ADC with multistage, differential pipelined architecture and integrated output error correction logic.
- Wide bandwidth differential sample-and-hold analog input amplifiers supporting various user-selectable input ranges.
- Integrated voltage reference to ease design considerations.
- Duty cycle stabilizer to compensate for variations in the ADC clock duty cycle.
- Fast overrange detect and signal monitor with serial output for simplified automatic gain control (AGC) functions.
- Proprietary differential input maintaining excellent SNR performance for input frequencies up to 450 MHz.
- Operation from a single 1.8 V supply and a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.
- Standard serial port interface (SPI) for setup and control, including data formatting, clock DCS, power-down, test modes, and voltage reference mode.
- Pin compatibility with other ADC models for easy migration.
- Flexible power-down options for significant power savings.
Applications
- Communications systems.
- Diversity radio systems.
- Multimode digital receivers (3G, GSM, EDGE, WCDMA, CDMA2000, WiMAX, TD-SCDMA).
Q & A
- What is the resolution of the AD9627BCPZ-125 ADC?
The AD9627BCPZ-125 has a resolution of 12 bits.
- What are the sample rates supported by the AD9627BCPZ-125?
The AD9627BCPZ-125 supports sample rates of 80 MSPS, 105 MSPS, 125 MSPS, and 150 MSPS.
- What is the operating supply voltage of the AD9627BCPZ-125?
The operating supply voltage is 1.8 V.
- What types of output interfaces are available on the AD9627BCPZ-125?
The AD9627BCPZ-125 supports CMOS and LVDS output interfaces.
- What is the power dissipation of the AD9627BCPZ-125 at 125 MSPS?
The power dissipation is approximately 750 mW at 125 MSPS.
- Does the AD9627BCPZ-125 have an integrated voltage reference?
Yes, the AD9627BCPZ-125 has an integrated voltage reference.
- What is the purpose of the duty cycle stabilizer in the AD9627BCPZ-125?
The duty cycle stabilizer compensates for variations in the ADC clock duty cycle to maintain excellent performance.
- How does the fast overrange detect feature work in the AD9627BCPZ-125?
The fast overrange detect feature outputs four bits of input level information with very short latency to quickly detect overrange conditions.
- What is the signal monitor block used for in the AD9627BCPZ-125?
The signal monitor block allows monitoring of the composite magnitude of the incoming signal to aid in setting the gain to optimize the dynamic range of the overall system.
- Is the AD9627BCPZ-125 compatible with other ADC models for easy migration?
Yes, the AD9627BCPZ-125 is pin-compatible with other ADC models such as the AD9640, AD9627-11, and AD9600.
