Overview
The AD9627BCPZ-105 is a dual, 12-bit analog-to-digital converter (ADC) produced by Analog Devices Inc. This component is designed to support communications applications where low cost, small size, and versatility are essential. The AD9627 features a multistage, differential pipelined architecture with integrated output error correction logic, ensuring high performance and accuracy. Each ADC includes wide bandwidth differential sample-and-hold analog input amplifiers that support various user-selectable input ranges. An integrated voltage reference simplifies design considerations, and a duty cycle stabilizer compensates for variations in the ADC clock duty cycle, maintaining excellent performance.
Key Specifications
Parameter | Unit | Min | Typ | Max |
---|---|---|---|---|
SIGNAL-TO-NOISE RATIO (SNR) @ 70 MHz, 25°C | dB | 69.4 | 69.5 | 69.6 |
SIGNAL-TO-NOISE AND DISTORTION (SINAD) @ 70 MHz, 25°C | dB | 69.0 | 69.1 | 69.2 |
Input Clock Rate | MHz | 625 | - | 625 |
Conversion Rate (DCS Enabled) | MSPS | 20 | - | 105 |
CLK Period—Divide-by-1 Mode (tCLK) | ns | 9.5 | - | 12.5 |
Input Resistance | kΩ | 26 | - | 26 |
Input Capacitance | pF | 5 | - | 5 |
High Level Output Voltage (CMOS Mode, DRVDD = 3.3 V, IOH = 50 μA) | V | 3.25 | 3.29 | - |
Low Level Output Voltage (CMOS Mode, DRVDD = 3.3 V, IOL = 1.6 mA) | V | 0.05 | 0.2 | - |
Key Features
- Dual, 12-bit analog-to-digital converter with sample rates of 80 MSPS, 105 MSPS, 125 MSPS, and 150 MSPS.
- 1.8 V analog supply operation and 1.8 V to 3.3 V CMOS or LVDS output supply.
- Integrated output error correction logic and multistage, differential pipelined architecture.
- Wide bandwidth differential sample-and-hold analog input amplifiers with user-selectable input ranges.
- Integrated voltage reference and duty cycle stabilizer to maintain performance.
- Fast overrange detection and signal monitor block with serial output.
- Integer 1-to-8 input clock divider and IF sampling frequencies up to 450 MHz.
- Low power consumption: 820 mW at 150 MSPS.
Applications
- Communications systems where low cost, small size, and versatility are crucial.
- Automatic gain control (AGC) in system receivers.
- Industrial instrumentation and high-frequency signal processing.
- Radar and defense systems requiring high-speed ADCs.
- Medical imaging and diagnostic equipment.
Q & A
- What is the maximum sample rate of the AD9627BCPZ-105?
The maximum sample rate of the AD9627BCPZ-105 is 105 MSPS.
- What is the signal-to-noise ratio (SNR) of the AD9627BCPZ-105 at 70 MHz input frequency?
The SNR at 70 MHz input frequency is approximately 69.4 dB to 69.6 dB.
- What are the supported output modes for the AD9627BCPZ-105?
The AD9627BCPZ-105 supports CMOS and LVDS output modes.
- What is the power consumption of the AD9627BCPZ-105 at 105 MSPS?
The power consumption at 105 MSPS is approximately 750 mW.
- Does the AD9627BCPZ-105 have an integrated voltage reference?
Yes, the AD9627BCPZ-105 has an integrated voltage reference.
- What is the input resistance of the AD9627BCPZ-105?
The input resistance is 26 kΩ.
- What is the purpose of the duty cycle stabilizer in the AD9627BCPZ-105?
The duty cycle stabilizer compensates for variations in the ADC clock duty cycle to maintain excellent performance.
- Can the AD9627BCPZ-105 be used in medical imaging applications?
Yes, the AD9627BCPZ-105 can be used in medical imaging and diagnostic equipment due to its high-speed and high-accuracy characteristics.
- What are the supported input clock divider modes for the AD9627BCPZ-105?
The AD9627BCPZ-105 supports integer 1-to-8 input clock divider modes.
- How does the fast detect feature work in the AD9627BCPZ-105?
The fast detect feature allows for fast overrange detection by outputting four bits of the ADC output, enabling quick identification of signal overrange conditions.