At Hot Chips, Intel Shares Details of Its Upcoming Xeon 6 SoC
Hot Chips 2024 last week was the place to be for high-performance computing enthusiasts, with noteworthy keynotes and product announcements coming from industry leaders. Among these announcements, Intel revealed its Xeon 6 SoC, built to address AI and compute needs on edge nodes and devices.
The Xeon 6 SoC combines Intel’s Redwood Lake core with edge-specific I/O features to create a high-performance solution for edge computing.
Many groups, including Intel, have set their sights on robust, power-efficient AI devices for edge applications. All About Circuits tuned into one of Intel's Hot Chips presentations led by Intel fellow Praveen Mosur to learn how the company's Xeon 6 SoC may help designers bring AI to the edge.
Shifting the AI Paradigm
With large AI models such as Copilot, ChatGPT, or Gemini here to stay, designers must employ distributed computing approaches to reap the highest utility from AI. Compared to centralized approaches, where all processing is done in a central server, distributed computing enables better decision-making and automation.
The Xeon 6 SoC block diagram highlights key aspects of the chip that can be used to address edge applications where more processing power is needed.
Furthermore, edge AI may be the only solution to advanced cases where network connectivity may be lacking.
“We believe that the edge is the next frontier in digital transformation,” Mosur said. “AI is further supercharging this transformation.”
Balancing Performance and SWaP
Intel’s newest SoC comes in two packages, four channels and eight channels, and includes many features to support this digital transformation. For one, the Xeon 6 SoC has over a 3× higher core count and memory bandwidth, leading to a 2.5× increase in I/O performance. In addition, the integrated 200-G Ethernet PHY, 50G SERDES, and cryptography/compression features double Ethernet throughput, ensuring that data latency is not responsible for bottlenecks.
The Xeon 6 SoC uses advanced packaging technology and a chiplet architecture to minimize latency while ensuring optimal performance across the compute and I/O chiplets.
The Xeon 6 SoC also includes many features to accelerate AI computing. Compared to the last-gen Xeon D 2700, the Xeon 7 SoC has kept the vector neural network instructions and has supplemented them with Intel Advanced Matrix Extensions (AMX).
“AMX extends the AI acceleration by adding hardware in the core of every single Redwood Cove—full hardware support for matrix multiplication,” Mosur said. “It has support for INT8, FP16, and VF16.”
Many of the improvements in the Xeon 6 SoC are likely credited to the advanced process node and the chiplet-based architecture. Using the Intel 4 process, Intel balanced transistor density and power consumption to address edge applications. The company's in-house EMIB technology supports high-bandwidth, low-latency interconnects to keep performance high.
“We use the extra transistor density to add a slew of accelerators that are optimized for the edge workloads that we were interested in,” Mosur said.
An Edge Processor for All
While the details surrounding the Xeon 6 SoC are few and far between, and it won’t be a one-size-fits-all solution, Intel claims this device strikes a happy medium between traditional MPUs and full-blown desktop processors.
A summary of the Xeon 6 SoC’s benefits. It can preprocess data to ease data center requirements.
If the Xeon 6 SoC can indeed accelerate AI training and deployment in edge scenarios, designers may soon find that previously inaccessible models are now standard issue at the edge.
“In a nutshell, our goal was to enable multiple edge systems based on one architecture—and we had to optimize this product for the edge,” Mosur said. “We added confidential AI to this product. We added multiple accelerators that supplement and complement the core. And we further integrated Ethernet into the device so system builders have the flexibility to design dense systems using the Xeon 6 SoC.”
