Overview
The CDCDB400RHBR, produced by Texas Instruments, is a 4-output clock buffer designed to meet the stringent performance requirements for various high-speed interfaces. This device is compliant with the DB800ZL specification and supports PCIe Gen 1 to Gen 6, QuickPath Interconnect (QPI), UPI, SAS, and SATA reference clocks in CC, SRNS, or SRIS architectures. It features low additive jitter and low propagation delay, making it ideal for applications requiring precise clock distribution.
Key Specifications
| Parameter | Min | Max | Unit | |
|---|---|---|---|---|
| VDD IO, Core supply voltage | 3 | 3.3 | 3.6 | V |
| VDD_R Input supply voltage | 3 | 3.3 | 3.6 | V |
| Ta Ambient temperature | -40 | 105 | °C | |
| Differential impedance (Default setting, 85 Ω) | 81 | 85 | 89 | Ω |
| Differential impedance (Output impedance selection bit =1, 100 Ω) | 95 | 100 | 105 | Ω |
| Additive jitter | 100 | 160 | fs, RMS | |
| ESD Ratings (Human body model) | ±3500 | V | ||
| ESD Ratings (Charged device model) | ±1000 | V | ||
| Package | 32-pin VQFN | |||
| Body size | 5.00 mm × 5.00 mm |
Key Features
- Low Additive Jitter and Propagation Delay: Designed to meet strict performance requirements with low additive jitter and propagation delay.
- Programmable Output Impedance: Integrated termination can be programmed for either 85 Ω or 100 Ω to match various board impedances.
- Output Slew Rate Control: Allows adjustment of output slew rate to compensate for increased output trace length.
- SMBus Interface: Supports SMBus version 2.0 for individual enable/disable of each output and other configuration settings.
- Hardware Output Enable Controls: Four hardware output enable (OE#) controls for each output channel.
- Fail-Safe Input Operation: Supports fail-safe input operation, allowing device inputs to be driven before VDD is applied without damage.
Applications
- Storage Area Networks and Host Bus Adapters: Ideal for storage area networks and host bus adapter cards.
- Network Attached Storage: Suitable for network attached storage applications.
- Hardware Accelerators: Used in hardware accelerators and rack servers.
- Communications Switches: Applicable in communications switches and computer on modules.
- Medical Equipment: Can be used in CT and PET scanners.
- Rugged PCs and Laptops: Suitable for rugged PC laptops.
Q & A
- What is the CDCDB400RHBR used for?
The CDCDB400RHBR is a 4-output clock buffer used for distributing reference clocks for PCIe Gen 1 to Gen 6, QPI, UPI, SAS, and SATA interfaces.
- What are the key features of the CDCDB400RHBR?
Key features include low additive jitter, programmable output impedance, output slew rate control, SMBus interface, and hardware output enable controls.
- What is the operating temperature range of the CDCDB400RHBR?
The operating temperature range is from -40°C to 105°C.
- What is the package type and size of the CDCDB400RHBR?
The device is packaged in a 32-pin VQFN package with a body size of 5.00 mm × 5.00 mm.
- How does the SMBus interface work on the CDCDB400RHBR?
The SMBus interface allows individual enable/disable of each output and other configuration settings. It is active only when CKPWRGD_PD# = 1.
- What are the ESD ratings for the CDCDB400RHBR?
The ESD ratings are ±3500 V for the human body model and ±1000 V for the charged device model.
- Can the output impedance of the CDCDB400RHBR be adjusted?
Yes, the output impedance can be programmed for either 85 Ω or 100 Ω.
- What applications is the CDCDB400RHBR suitable for?
It is suitable for storage area networks, network attached storage, hardware accelerators, communications switches, medical equipment, and rugged PCs and laptops.
- Does the CDCDB400RHBR support fail-safe input operation?
Yes, it supports fail-safe input operation, allowing device inputs to be driven before VDD is applied without damage.
- How are the output channels controlled on the CDCDB400RHBR?
Each output channel can be individually enabled or disabled by SMBus control register bits and corresponding hardware OE# pins.
