Overview
The CDCDB400RHBT is a high-performance clock buffer designed by Texas Instruments. This device is a 4-output LP-HCSL (Low-Power High-Speed Current Steering Logic) clock buffer, compliant with the DB800ZL specification. It is capable of distributing reference clocks for various high-speed interfaces including PCIe Gen 1 to Gen 6, QuickPath Interconnect (QPI), UPI, SAS, and SATA. The CDCDB400RHBT is packaged in a compact 5-mm × 5-mm, 32-pin VQFN package, making it suitable for a wide range of applications requiring precise clock distribution.
Key Specifications
| Parameter | Value |
|---|---|
| Package Type | VQFN (RHB) |
| Number of Pins | 32 |
| Operating Temperature Range (°C) | -40 to 105 |
| Supply Voltage (V) | 3.3 (core and IO) |
| Maximum Supply Voltage (V) | 3.6 |
| Number of Outputs | 4 |
| Output Frequency (max) (MHz) | 250 |
| Additive Phase Jitter after PCIe Gen 6 Filter (fs, RMS) | 20 |
| Additive Phase Jitter after PCIe Gen 5 Filter (fs, RMS) | 25 |
| Additive Phase Jitter after DB2000Q Filter (fs, RMS) | 38 |
| Output-to-Output Skew (ps) | < 50 |
| Input-to-Output Delay (ns) | < 3 |
| Current Consumption (mA) | 46 (maximum) |
Key Features
- 4 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations
- 4 hardware output enable (OE#) controls
- Supports Common Clock (CC) and Individual Reference (IR) architectures
- Spread spectrum-compatible
- Fail-safe input
- Programmable output slew rate control
- 3 selectable SMBus addresses
- Hardware-controlled low power mode (PD#)
- Compact 5-mm × 5-mm, 32-pin VQFN package
Applications
The CDCDB400RHBT is designed for use in various high-speed data transfer applications, including:
- PCIe Gen 1 to Gen 6 interfaces
- QuickPath Interconnect (QPI)
- UPI (Ultra Path Interconnect)
- SAS (Serial Attached SCSI) and SATA (Serial Advanced Technology Attachment) interfaces
- Server and storage systems requiring precise clock distribution
- High-performance computing and networking equipment
Q & A
- What is the CDCDB400RHBT?
The CDCDB400RHBT is a 4-output LP-HCSL clock buffer designed for distributing reference clocks in high-speed interfaces such as PCIe Gen 1 to Gen 6, QPI, UPI, SAS, and SATA.
- What is the package type and size of the CDCDB400RHBT?
The CDCDB400RHBT is packaged in a 5-mm × 5-mm, 32-pin VQFN package.
- What are the operating temperature ranges for the CDCDB400RHBT?
The operating temperature range is -40°C to 105°C.
- What is the maximum output frequency of the CDCDB400RHBT?
The maximum output frequency is 250 MHz.
- Does the CDCDB400RHBT support spread spectrum clocking?
- How many SMBus addresses are selectable on the CDCDB400RHBT?
- What is the maximum current consumption of the CDCDB400RHBT?
- Does the CDCDB400RHBT have hardware-controlled low power mode?
- What are the typical additive phase jitter values for the CDCDB400RHBT?
The additive phase jitter values are 20 fs (RMS) for PCIe Gen 6, 25 fs (RMS) for PCIe Gen 5, and 38 fs (RMS) for DB2000Q filter.
- What is the output-to-output skew of the CDCDB400RHBT?
