Overview
The CDC3RL02YFPR is a dual-channel clock fan-out buffer produced by Texas Instruments. This device is designed to provide low phase noise and minimal additive jitter, making it ideal for applications requiring precise clock signal distribution. The CDC3RL02YFPR accepts both square and sine wave inputs and can buffer these signals to multiple outputs, eliminating the need for an AC coupling capacitor. It is particularly suited for use in portable end-equipment such as mobile phones, where low power consumption and minimal EMI are crucial.
Key Specifications
| Parameter | Value | Unit |
|---|---|---|
| Manufacturer | Texas Instruments | |
| Package Type | DSBGA (Wafer-Level Chip-Scale Package) | |
| Number of Pins | 8 | |
| Logic Function | Fanout Buffer | |
| Max Frequency | 52 MHz | |
| Min Supply Voltage | 2.3 V | |
| Max Supply Voltage | 5.5 V | |
| Min Operating Temperature | -40°C | |
| Max Operating Temperature | 85°C | |
| Number of Inputs | 1 | |
| Number of Outputs | 2 | |
| Output Jitter (RMS) | 0.37 ps | |
| Additive Phase Noise at 10kHz Offset | -149 dBc/Hz | |
| Package Size | 0.8mm x 1.6mm | |
| Surface Mount | Yes | |
| RoHS Compliance | Yes |
Key Features
- Low Additive Noise: The CDC3RL02YFPR features low additive phase noise of –149 dBc/Hz at 10 kHz offset and 0.37 ps (RMS) output jitter, ensuring high signal quality.
- Adaptive Clock Output Buffers: The device offers controlled slew-rate over a wide capacitive loading range, minimizing EMI emissions and maintaining signal integrity.
- Integrated LDO Voltage Regulator: The device includes a Low-Drop-Out (LDO) voltage regulator that accepts input voltages from 2.3V to 5.5V and outputs 1.8V, 50mA, which is externally available to power peripheral devices.
- Ultra-Small Package: The CDC3RL02YFPR is packaged in an ultra-small 8-bump YFP (Wafer-Level Chip-Scale Package) with a 0.4mm pitch, ideal for space-constrained designs.
- Low Power Consumption: The device enters a low power shutdown mode when disabled, consuming less than 1 μA from the battery.
- Accepts Square or Sine Wave Inputs: The CDC3RL02YFPR can accept both square and sine wave inputs, eliminating the need for an AC coupling capacitor.
Applications
The CDC3RL02YFPR is designed for use in various portable and mobile applications, including:
- Mobile phones and other handheld devices.
- Tablets and other portable electronics.
- Wearable devices such as smartwatches and fitness trackers.
- Other battery-powered devices requiring low noise clock signal distribution.
Q & A
- What is the maximum frequency supported by the CDC3RL02YFPR?
The CDC3RL02YFPR supports a maximum frequency of 52 MHz.
- What is the smallest acceptable sine wave input for the CDC3RL02YFPR?
The smallest acceptable sine wave input is a 0.3V signal (peak-to-peak).
- What is the output jitter of the CDC3RL02YFPR?
The output jitter is 0.37 ps (RMS).
- What is the additive phase noise at 10 kHz offset for the CDC3RL02YFPR?
The additive phase noise at 10 kHz offset is –149 dBc/Hz.
- What type of package does the CDC3RL02YFPR use?
The CDC3RL02YFPR is packaged in an 8-bump DSBGA (Wafer-Level Chip-Scale Package) with a 0.4mm pitch.
- Does the CDC3RL02YFPR have an integrated voltage regulator?
Yes, the CDC3RL02YFPR includes an integrated Low-Drop-Out (LDO) voltage regulator that outputs 1.8V, 50mA.
- What is the operating temperature range of the CDC3RL02YFPR?
The operating temperature range is from –40°C to 85°C.
- Is the CDC3RL02YFPR RoHS compliant?
Yes, the CDC3RL02YFPR is RoHS compliant.
- How many clock request inputs does the CDC3RL02YFPR have?
The CDC3RL02YFPR has two clock request inputs (CLK_REQ1 and CLK_REQ2).
- What is the power consumption in shutdown mode?
In shutdown mode, the device consumes less than 1 μA from the battery.
