Overview
The 74HC138DR2G, produced by ON Semiconductor, is a high-performance silicon-gate CMOS 1-of-8 decoder/demultiplexer. This device is identical in pinout to the LS138 and is designed to decode three binary weighted address inputs (A0, A1, and A2) to eight mutually exclusive active-low outputs (Y0 to Y7). It features three enable inputs (E1, E2, and E3) that facilitate demultiplexing, cascading, and chip-selecting functions. The device is compatible with standard CMOS outputs and, with pullup resistors, can also interface with LSTTL outputs.
Key Specifications
| Parameter | Conditions | Min | Typ | Max | Unit |
|---|---|---|---|---|---|
| VCC Supply Voltage | 2.0 | 5.0 | 6.0 | V | |
| VI Input Voltage | 0 | VCC | V | ||
| VO Output Voltage | 0 | VCC | V | ||
| Tamb Ambient Temperature | -40 | 25 | 125 | °C | |
| VIH High-Level Input Voltage | VCC = 2.0 V | 1.5 | V | ||
| VIH High-Level Input Voltage | VCC = 4.5 V | 3.15 | V | ||
| VIL Low-Level Input Voltage | VCC = 2.0 V | 0.8 | 0.5 | V | |
| VIL Low-Level Input Voltage | VCC = 4.5 V | 2.1 | 1.35 | V | |
| tPLH, tPHL Maximum Propagation Delay | VCC = 2.0 V | 150 | ns | ||
| tPLH, tPHL Maximum Propagation Delay | VCC = 4.5 V | 38 | ns | ||
| ICC Maximum Quiescent Supply Current | VCC = 5.0 V, IO = 0 A | 160 | μA |
Key Features
- Output Drive Capability: 10 LSTTL Loads
- Outputs Directly Interface to CMOS, NMOS, and TTL
- Operating Voltage Range: 2.0 to 6.0 V
- Low Input Current: 1.0 μA
- High Noise Immunity Characteristic of CMOS Devices
- In Compliance with the Requirements Defined by JEDEC Standard No. 7A
- Demultiplexing Capability
- Multiple Input Enable for Easy Expansion
- Ideal for Memory Chip Select Decoding
- Active LOW Mutually Exclusive Outputs
- ESD Protection: HBM JESD22-A114F exceeds 2000 V, MM JESD22-A115-A exceeds 200 V
- Multiple Package Options
Applications
- Memory Chip Select Decoding
- Demultiplexing Functions
- Cascading and Chip-Selecting Functions
- Level Conversion for Interfacing TTL or NMOS Outputs to High-Speed CMOS Inputs
- General Digital Logic and Control Circuits
Q & A
- What is the primary function of the 74HC138DR2G?
The primary function of the 74HC138DR2G is to decode three binary weighted address inputs to eight mutually exclusive active-low outputs, and it can also function as a demultiplexer.
- What is the operating voltage range of the 74HC138DR2G?
The operating voltage range of the 74HC138DR2G is from 2.0 to 6.0 V.
- How many enable inputs does the 74HC138DR2G have?
The 74HC138DR2G has three enable inputs (E1, E2, and E3), with two active-low and one active-high.
- What is the maximum propagation delay for the 74HC138DR2G at VCC = 4.5 V?
The maximum propagation delay for the 74HC138DR2G at VCC = 4.5 V is approximately 38 ns.
- Is the 74HC138DR2G compatible with TTL outputs?
Yes, the 74HC138DR2G is compatible with TTL outputs, especially when using the 74HCT138 version which is designed for TTL level inputs.
- What is the maximum quiescent supply current for the 74HC138DR2G at VCC = 5.0 V?
The maximum quiescent supply current for the 74HC138DR2G at VCC = 5.0 V is 160 μA.
- Does the 74HC138DR2G have ESD protection?
Yes, the 74HC138DR2G has ESD protection with HBM JESD22-A114F exceeding 2000 V and MM JESD22-A115-A exceeding 200 V.
- Can the 74HC138DR2G be used for level conversion?
Yes, the 74HCT138 version of the device can be used as a level converter for interfacing TTL or NMOS outputs to high-speed CMOS inputs.
- What are the typical package options for the 74HC138DR2G?
The 74HC138DR2G is available in SOIC-16 and TSSOP-16 packages.
- How does the 74HC138DR2G handle unused inputs and outputs?
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC), and unused outputs must be left open.
