Overview
The PCA9515D,112, produced by NXP USA Inc., is a BiCMOS integrated circuit designed for use in I2C-bus and SMBus systems. This component is intended to extend the capabilities of I2C-bus systems by buffering both the data (SDA) and clock (SCL) lines, thereby enabling the connection of more devices or the extension of bus lengths. The PCA9515 retains all the operating modes and features of the I2C-bus system, making it a versatile solution for various applications requiring I2C-bus or SMBus compatibility.
Key Specifications
| Parameter | Conditions | Min | Typ | Max | Unit |
|---|---|---|---|---|---|
| VCC supply voltage | 3.0 | 3.3 | 3.6 | V | |
| HIGH-level supply current (both channels) | VCC = 3.6 V; SDAn = SCLn = VCC | 5 | mA | ||
| LOW-level supply current (both channels) | VCC = 3.6 V; one SDA and one SCL = GND | 5 | mA | ||
| Clock frequency | 0 | 400 | kHz | ||
| ESD protection | 2000 | V HBM per JESD22-A114 | |||
| I2C-bus pins (SCLn, SDAn, EN) | 5.5 | V tolerant |
Key Features
- 2-channel, bidirectional buffer for I2C-bus and SMBus systems
- Supports Standard-mode and Fast-mode I2C-bus devices and multiple masters
- Active HIGH repeater enable input with internal pull-up
- Open-drain input/outputs
- Lock-up free operation
- Supports arbitration and clock stretching across the repeater
- Powered-off high-impedance I2C-bus pins
- Operating supply voltage range of 3.0 V to 3.6 V
Applications
The PCA9515D,112 is suitable for various applications where I2C-bus or SMBus systems need to be extended or isolated. This includes:
- Extending I2C-bus lengths to accommodate more devices
- Isolating two halves of a bus to prevent interference or improve system reliability
- Running two buses at different voltage levels (e.g., 5 V and 3.3 V) or different clock frequencies (e.g., 400 kHz and 100 kHz)
- Improving system performance by buffering the data and clock lines to reduce capacitance effects
Q & A
- What is the primary function of the PCA9515D,112?
The PCA9515D,112 is a BiCMOS integrated circuit designed to extend and buffer I2C-bus and SMBus systems by buffering both the data (SDA) and clock (SCL) lines.
- What are the operating voltage ranges for the PCA9515D,112?
The operating supply voltage range is from 3.0 V to 3.6 V.
- What is the maximum clock frequency supported by the PCA9515D,112?
The maximum clock frequency supported is 400 kHz.
- Does the PCA9515D,112 support multiple masters on the I2C-bus?
- What is the purpose of the EN pin on the PCA9515D,112?
The EN pin is an active HIGH repeater enable input with an internal pull-up, allowing the user to select when the repeater is active.
- Is the PCA9515D,112 protected against ESD?
- Can the PCA9515D,112 be used in series with other I2C-bus repeaters?
The PCA9515D,112 cannot be used in series with certain other repeaters like PCA9510A/9511A/9513A/9514A and PCA9512A, but it can be used in series with itself or other compatible repeaters.
- What is the significance of using the PCA9515A instead of the PCA9515 in some applications?
The PCA9515A has a wider voltage range and should be used in applications where power is secured to the repeater but an active bus remains on either set of SCLn/SDAn pins to prevent increased bus loading.
- How does the PCA9515D,112 handle arbitration and clock stretching?
- What is the typical capacitance of the SCLn/SDAn inputs when VCC = 0 V?
