Overview
The ADF4001BCPZ from Analog Devices Inc. is a high-performance clock generator and phase-locked loop (PLL) synthesizer. This device is designed to provide low noise, stable reference signals, making it ideal for various clock generation and frequency synthesis applications. The ADF4001 features a low noise digital phase frequency detector (PFD), a precision charge pump, and programmable reference and N counters. It supports a wide range of frequencies and is compatible with external loop filters and voltage-controlled oscillators (VCOs) or voltage-controlled crystal oscillators (VCXOs).
Key Specifications
| Parameter | Value | Unit | Test Conditions |
|---|---|---|---|
| Operating Temperature Range | –40°C to +85°C | °C | B Version |
| Power Supply Voltage (AVDD, DVDD) | 2.7 V to 5.5 V | V | |
| Charge Pump Supply Voltage (VP) | AVDD ≤ VP ≤ 6.0 V | V | |
| Typical Operating Current | 4.5 mA | mA | AVDD = DVDD = 3 V, TA = 25°C |
| Low Power Sleep Mode Current | 1 µA | µA | TA = 25°C |
| RF Input Frequency (3 V) | 5 MHz to 165 MHz | MHz | |
| RF Input Frequency (5 V) | 10 MHz to 200 MHz | MHz | |
| Phase Noise Floor | –161 dBc/Hz @ 200 kHz | dBc/Hz | |
| Package Type | 20-Lead LFCSP |
Key Features
- Low noise digital phase frequency detector (PFD)
- Precision charge pump with programmable currents
- Programmable 13-bit N counter and 14-bit reference counter
- 3-wire serial interface
- Hardware and software power-down mode
- Analog and digital lock detect
- Ultralow phase noise performance
- Separate charge pump supply (VP) for extended tuning voltage in 5 V systems
Applications
- Clock generation for PLLs requiring low noise and stable reference signals
- Low frequency PLLs
- Low jitter clock sources
- Clock smoothing and frequency translation
- SONET, ATM, ADM, DSLAM, and SDM systems
Q & A
- What is the operating temperature range of the ADF4001BCPZ?
The operating temperature range is –40°C to +85°C.
- What is the typical operating current of the ADF4001BCPZ?
The typical operating current is 4.5 mA at AVDD = DVDD = 3 V and TA = 25°C.
- What is the phase noise floor of the ADF4001BCPZ?
The phase noise floor is –161 dBc/Hz at 200 kHz offset frequency.
- What types of counters are available in the ADF4001BCPZ?
The device features a 13-bit N counter and a 14-bit reference counter.
- What is the package type of the ADF4001BCPZ?
The package type is a 20-Lead LFCSP.
- Can the ADF4001BCPZ be used in low power sleep mode?
Yes, it has a low power sleep mode with a current of 1 µA at TA = 25°C.
- What is the maximum RF input frequency for the ADF4001BCPZ at 5 V supply?
The maximum RF input frequency is 200 MHz at 5 V supply.
- Is the ADF4001BCPZ compatible with external loop filters and VCOs/VCXOs?
Yes, it is compatible with external loop filters and VCOs/VCXOs.
- What is the typical phase noise performance at the VCXO output?
The typical phase noise performance at the VCXO output is –99 dBc/Hz at 1 kHz offset and 200 kHz PFD frequency.
- Does the ADF4001BCPZ support a 3-wire serial interface?
Yes, it supports a 3-wire serial interface).
