Overview
The AD9650BCPZ-105 is a dual, 16-bit analog-to-digital converter (ADC) designed by Analog Devices Inc. This device is optimized for digitizing high-frequency, wide dynamic range signals with input frequencies up to 300 MHz. The AD9650 features a multistage, differential pipelined architecture with integrated output error correction logic, ensuring high performance and accuracy. Each ADC includes wide bandwidth, differential sample-and-hold analog input amplifiers and a shared integrated voltage reference, simplifying design considerations. The device operates from a single 1.8 V supply and supports 1.8 V CMOS or LVDS output drivers.
Key Specifications
| Parameter | Min | Typ | Max | Unit |
|---|---|---|---|---|
| SIGNAL-TO-NOISE RATIO (SNR) at 30 MHz input and 105 MSPS | 81.5 | 82 | 82 | dBFS |
| SIGNAL-TO-NOISE RATIO (SNR) at 9.7 MHz input and 25 MSPS | 83 | 83 | 83 | dBFS |
| SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) at 30 MHz input and 105 MSPS | 80.4 | 81.2 | 82 | dBFS |
| SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) at 9.7 MHz input and 25 MSPS | 82.2 | 82 | 82 | dBFS |
| SPURIOUS FREE DYNAMIC RANGE (SFDR) at 30 MHz input and 105 MSPS | 90 | 90 | 90 | dBc |
| SPURIOUS FREE DYNAMIC RANGE (SFDR) at 9.7 MHz input and 25 MSPS | 95 | 95 | 95 | dBc |
| Power Consumption per Channel at 105 MSPS | 328 | mW | ||
| Power Consumption per Channel at 25 MSPS | 119 | mW | ||
| Sample Rate | 25 | 105 | MSPS | |
| Input Clock Rate | 200 | 640 | MHz | |
| Operating Temperature Range | -40 | 85 | °C |
Key Features
- 1.8 V analog supply operation and 1.8 V CMOS or LVDS output supply
- High SNR and SFDR performance: 82 dBFS at 30 MHz input and 105 MSPS, and 95 dBc SFDR at 9.7 MHz input and 25 MSPS
- Low power consumption: 328 mW per channel at 105 MSPS and 119 mW per channel at 25 MSPS
- Integer 1-to-8 input clock divider and IF sampling frequencies up to 300 MHz
- On-chip dither option for improved SFDR performance with low power analog input
- Proprietary differential input maintaining excellent SNR performance for input frequencies up to 300 MHz
- Duty cycle stabilizer to compensate for variations in the ADC clock duty cycle
- Flexible power-down options for significant power savings
- 3-wire SPI-compatible serial interface for setup and control
- Pin compatible with other dual ADC families like AD9268, AD9269, AD9251, AD9231, and AD9204
Applications
- Industrial instrumentation
- X-Ray, MRI, and ultrasound equipment
- High speed pulse acquisition
- Chemical and spectrum analysis
- Direct conversion receivers
- Multimode digital receivers
- Smart antenna systems
- General-purpose software radios
Q & A
- What is the maximum sample rate of the AD9650BCPZ-105?
The maximum sample rate of the AD9650BCPZ-105 is 105 MSPS.
- What is the power consumption per channel at 105 MSPS?
The power consumption per channel at 105 MSPS is 328 mW.
- What are the supported output formats for the AD9650BCPZ-105?
The AD9650BCPZ-105 supports 1.8 V CMOS or LVDS output formats.
- What is the operating temperature range of the AD9650BCPZ-105?
The operating temperature range is from -40°C to +85°C.
- Does the AD9650BCPZ-105 have on-chip dither?
Yes, the AD9650BCPZ-105 has an optional on-chip dither for improved SFDR performance.
- What is the bandwidth of the differential analog input amplifiers?
The bandwidth of the differential analog input amplifiers is 500 MHz.
- How is the AD9650BCPZ-105 programmed for setup and control?
The AD9650BCPZ-105 is programmed using a 3-wire SPI-compatible serial interface.
- Is the AD9650BCPZ-105 pin compatible with other ADCs?
Yes, it is pin compatible with other dual ADC families like AD9268, AD9269, AD9251, AD9231, and AD9204.
- What are some of the applications of the AD9650BCPZ-105?
Applications include industrial instrumentation, X-Ray, MRI, and ultrasound equipment, high speed pulse acquisition, and more.
- Does the AD9650BCPZ-105 support flexible power-down options?
Yes, it supports flexible power-down options for significant power savings.
