Overview
The AD9650BCPZ-65 is a dual, 16-bit analog-to-digital converter (ADC) produced by Analog Devices Inc. This device is designed to digitize high-frequency, wide dynamic range signals with input frequencies up to 300 MHz. The AD9650 features a multistage, differential pipelined architecture with integrated output error correction logic, ensuring high performance and accuracy. Each ADC includes wide bandwidth, differential sample-and-hold analog input amplifiers and a shared integrated voltage reference, simplifying design considerations. The device operates from a single 1.8 V supply and supports 1.8 V CMOS or LVDS output drivers.
Key Specifications
| Parameter | Min | Typ | Max | Unit |
|---|---|---|---|---|
| SIGNAL-TO-NOISE RATIO (SNR) at 9.7 MHz input and 65 MSPS data rate | 82.5 | 82 | 82 | dBFS |
| SIGNAL-TO-NOISE RATIO (SNR) at 30 MHz input and 65 MSPS data rate | 81.5 | 82 | 82 | dBFS |
| SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) at 9.7 MHz input and 65 MSPS data rate | 82.2 | 82 | 82 | dBFS |
| SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) at 30 MHz input and 65 MSPS data rate | 80 | 81.2 | 82 | dBFS |
| SPURIOUS FREE DYNAMIC RANGE (SFDR) at 30 MHz input and 65 MSPS data rate | 90 | - | - | dBc |
| Power Consumption per Channel at 65 MSPS | - | 328 | - | mW |
| Input Clock Rate | - | 520 | 640 | MHz |
| Conversion Rate with DCS Enabled | - | 65 | - | MSPS |
| Analog Input Range | - | 2.7 | - | V p-p |
| Operating Temperature Range | -40 | - | 85 | °C |
Key Features
- 1.8 V analog supply operation and 1.8 V CMOS or LVDS output supply
- High SNR: 82 dBFS at 30 MHz input and 65 MSPS data rate, 83 dBFS at 9.7 MHz input and 65 MSPS data rate
- High SFDR: 90 dBc at 30 MHz input and 65 MSPS data rate, 95 dBc at 9.7 MHz input and 65 MSPS data rate
- Low power consumption: 328 mW per channel at 65 MSPS
- Integer 1-to-8 input clock divider
- On-chip dither option for improved SFDR performance with low power analog input
- Proprietary differential input maintaining excellent SNR performance for input frequencies up to 300 MHz
- Duty cycle stabilizer to compensate for variations in the ADC clock duty cycle
- Flexible power-down options for significant power savings
- 3-wire SPI-compatible serial interface for setup and control
- Pin compatible with other dual ADC families like AD9268, AD9269, AD9251, AD9231, and AD9204
Applications
- Industrial instrumentation
- X-Ray, MRI, and ultrasound equipment
- High speed pulse acquisition
- Chemical and spectrum analysis
- Direct conversion receivers
- Multimode digital receivers
- Smart antenna systems
- General-purpose software radios
Q & A
- What is the maximum input frequency the AD9650BCPZ-65 can handle?
The AD9650BCPZ-65 can handle input frequencies up to 300 MHz.
- What are the power consumption and supply voltages for the AD9650BCPZ-65?
The device operates from a single 1.8 V supply and consumes 328 mW per channel at 65 MSPS.
- What types of output interfaces does the AD9650BCPZ-65 support?
The AD9650BCPZ-65 supports 1.8 V CMOS or LVDS output interfaces.
- What is the significance of the duty cycle stabilizer in the AD9650BCPZ-65?
The duty cycle stabilizer compensates for variations in the ADC clock duty cycle, ensuring excellent performance.
- How is the AD9650BCPZ-65 programmed for setup and control?
The device is programmed using a 3-wire SPI-compatible serial interface.
- What are some of the key applications of the AD9650BCPZ-65?
Key applications include industrial instrumentation, X-Ray, MRI, and ultrasound equipment, high speed pulse acquisition, and general-purpose software radios.
- What is the operating temperature range of the AD9650BCPZ-65?
The operating temperature range is from -40°C to +85°C.
- Does the AD9650BCPZ-65 support on-chip dither?
Yes, the AD9650BCPZ-65 supports an on-chip dither option for improved SFDR performance.
- Is the AD9650BCPZ-65 pin compatible with other ADC families?
Yes, it is pin compatible with other dual ADC families like AD9268, AD9269, AD9251, AD9231, and AD9204.
- What is the package type of the AD9650BCPZ-65?
The device is available in a 64-lead LFCSP package.
