Overview
The AD9649BCPZ-65, produced by Analog Devices Inc., is a high-performance, monolithic, single-channel 14-bit analog-to-digital converter (ADC). It operates from a single 1.8 V analog power supply and features a separate digital output driver supply that can accommodate 1.8 V to 3.3 V logic families. This ADC is designed for low power consumption and ease of use, making it suitable for a variety of high-speed applications.
Key Specifications
| Parameter | Min | Typ | Max |
|---|---|---|---|
| Conversion Rate | 20 MSPS | - | 80 MSPS |
| Input Clock Rate | 80 MHz | - | 320 MHz |
| CLK Period, Divide-by-1 Mode (tCLK) | 12.5 ns | - | 50 ns |
| Aperture Delay (tA) | 1.0 ns | - | 1.0 ns |
| Aperture Uncertainty (Jitter, tJ) | 0.1 ps rms | - | 0.1 ps rms |
| Data Propagation Delay (tPD) | 3 ns | - | 3 ns |
| DCO Propagation Delay (tDCO) | 3 ns | - | 3 ns |
| Pipeline Delay (Latency) | 8 Cycles | - | 8 Cycles |
| Wake-Up Time | 350 µs | - | 350 µs |
| Operating Temperature Range | -40°C | - | +85°C |
| Package Type | 32-Lead LFCSP | - | - |
Key Features
- 1.8 V analog supply operation with separate 1.8 V to 3.3 V digital output driver supply
- High performance sample-and-hold circuit with 700 MHz bandwidth
- On-chip voltage reference and sample-and-hold circuit
- 2 V p-p differential analog input
- Low power consumption: 45 mW at 20 MSPS and 87 mW at 80 MSPS
- SNR: 74.3 dBFS at 9.7 MHz input and 71.5 dBFS at 200 MHz input
- SFDR: 93 dBc at 9.7 MHz input and 80 dBc at 200 MHz input
- DNL = ±0.35 LSB
- Serial port control options: offset binary, gray code, or twos complement data format
- Programmable clock and data alignment, and programmable digital test pattern generation
- Differential clock input with optional 1, 2, or 4 divide ratios
Applications
- Communications systems
- Diversity radio systems
- Multimode digital receivers (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA)
Q & A
- What is the AD9649BCPZ-65's conversion rate range?
The AD9649BCPZ-65 has a conversion rate range of 20 MSPS to 80 MSPS. - What is the operating voltage of the analog supply?
The analog supply operates at 1.8 V. - What are the supported digital output logic levels?
The digital output driver supports 1.8 V to 3.3 V CMOS levels. - What is the bandwidth of the sample-and-hold circuit?
The sample-and-hold circuit has a bandwidth of 700 MHz. - What are the power consumption levels at different sample rates?
The power consumption is 45 mW at 20 MSPS and 87 mW at 80 MSPS. - What data formats are supported by the AD9649BCPZ-65?
The AD9649BCPZ-65 supports offset binary, gray code, and twos complement data formats. - What is the package type of the AD9649BCPZ-65?
The AD9649BCPZ-65 is packaged in a 32-Lead LFCSP. - What is the operating temperature range of the AD9649BCPZ-65?
The operating temperature range is from -40°C to +85°C. - Does the AD9649BCPZ-65 support programmable digital test patterns?
Yes, it supports programmable digital test patterns, including built-in deterministic and pseudorandom patterns, as well as custom user-defined patterns. - Is the AD9649BCPZ-65 RoHS-compliant?
Yes, the AD9649BCPZ-65 is RoHS-compliant.
