Overview
The AD9268BCPZ-80 is a dual, 16-bit analog-to-digital converter (ADC) produced by Analog Devices Inc. This device is designed to support high-performance communications applications, offering a balance of high speed, low power consumption, small size, and versatility. The AD9268 features a multistage, differential pipelined architecture with integrated output error correction logic and wide bandwidth, differential sample-and-hold analog input amplifiers. It supports various user-selectable input ranges and includes an integrated voltage reference to simplify design considerations. A duty cycle stabilizer ensures excellent performance by compensating for variations in the ADC clock duty cycle.
Key Specifications
| Parameter | Min | Typ | Max | Unit |
|---|---|---|---|---|
| Supply Voltage (AVDD) | 1.7 | 1.8 | 1.9 | V |
| Supply Voltage (DRVDD) | 1.7 | 1.8 | 1.9 | V |
| Supply Current (IAVDD1) | 234 | 240 | 293 | mA |
| Supply Current (IDRVDD1) - 1.8 V CMOS | 35 | 45 | 55 | mA |
| Supply Current (IDRVDD1) - 1.8 V LVDS | 89 | 89 | 94 | mA |
| Power Consumption - DC Input | 420 | 450 | 565 | mW |
| Conversion Rate - DCS Enabled | 20 | 80 | 80 | MSPS |
| Clock Input Rate | 625 | 625 | 625 | MHz |
| CLK Period - Divide-by-1 Mode (tCLK) | 12.5 | 9.5 | 8 | ns |
| CLK Pulse Width High (tCH) - Divide-by-1 Mode, DCS Enabled | 3.75 | 6.25 | 8.75 | ns |
Key Features
- SNR = 78.2 dBFS @ 70 MHz and 125 MSPS
- SFDR = 88 dBc @ 70 MHz and 125 MSPS
- Low power: 750 mW @ 125 MSPS
- 1.8 V analog supply operation
- 1.8 V CMOS or LVDS output supply
- Integer 1-to-8 input clock divider
- IF sampling frequencies up to 300 MHz
- −153.6 dBm/Hz small-signal input noise with 200 Ω input impedance @ 70 MHz and 125 MSPS
- Optional on-chip dither for improved SFDR performance
- Programmable internal ADC voltage reference
- Flexible power-down options for significant power savings
- 3-wire SPI-compatible serial interface for setup and control
- Pin compatibility with AD9258, AD9251, AD9231, and AD9204 family of products
Applications
The AD9268 is designed to support a variety of high-performance communications applications, including:
- Wireless infrastructure
- Medical imaging
- Industrial instrumentation
- Aerospace and defense systems
- High-speed data acquisition systems
The device's versatility, low power consumption, and high-speed capabilities make it suitable for applications requiring precise and efficient analog-to-digital conversion.
Q & A
- What is the resolution and sample rate of the AD9268?
The AD9268 is a dual 16-bit ADC with sample rates of 80 MSPS, 105 MSPS, and 125 MSPS.
- What are the supply voltage requirements for the AD9268?
The AD9268 operates from a single 1.8 V analog supply (AVDD) and a separate 1.8 V digital output driver supply (DRVDD).
- What output formats are supported by the AD9268?
The AD9268 supports 1.8 V CMOS or LVDS output formats.
- How is the AD9268 programmed and controlled?
Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.
- What is the temperature range for the AD9268?
The AD9268 is specified over the industrial temperature range of −40°C to +85°C.
- What are the key features of the AD9268's architecture?
The AD9268 features a multistage, differential pipelined architecture with integrated output error correction logic and wide bandwidth, differential sample-and-hold analog input amplifiers.
- Does the AD9268 have any power-saving features?
Yes, the AD9268 has flexible power-down options that allow significant power savings when desired.
- What is the package type and pin count of the AD9268?
The AD9268 is available in a 64-lead LFCSP package.
- Is the AD9268 compatible with other ADC models from Analog Devices?
Yes, the AD9268 is pin compatible with the AD9258, AD9251, AD9231, and AD9204 family of products.
- What tools are available for evaluating the AD9268?
The AD9268-125EBZ evaluation board and software tools like VisualAnalog and SPI controller software are available for evaluating and configuring the device.
