Overview
The AD9268BCPZ-105, produced by Analog Devices Inc., is a dual, 16-bit analog-to-digital converter (ADC) designed for high-performance applications. This component is particularly suited for communications systems where low cost, small size, and versatility are crucial. The AD9268 features a multistage, differential pipelined architecture with integrated output error correction logic and wide bandwidth, differential sample-and-hold analog input amplifiers. It supports various user-selectable input ranges and includes an integrated voltage reference, enhancing design simplicity. The ADC also incorporates a duty cycle stabilizer to maintain excellent performance despite variations in the ADC clock duty cycle.
Key Specifications
| Parameter | Min | Typ | Max | Unit |
|---|---|---|---|---|
| Supply Voltage (AVDD) | 1.7 | 1.8 | 1.9 | V |
| Supply Voltage (DRVDD) | 1.7 | 1.8 | 1.9 | V |
| Supply Current (IAVDD1) | 300 | 390 | 400 | mA |
| Supply Current (IDRVDD1) - 1.8 V CMOS | 35 | 45 | 55 | mA |
| Supply Current (IDRVDD1) - 1.8 V LVDS | 89 | 94 | mA | |
| Power Consumption - DC Input | 590 | 750 | 777 | mW |
| Power Consumption - Sine Wave Input (DRVDD = 1.8 V CMOS Output Mode) | 485 | 608 | 800 | mW |
| Power Consumption - Sine Wave Input (DRVDD = 1.8 V LVDS Output Mode) | 582 | 685 | mW | |
| Input Clock Rate | 625 | MHz | ||
| Conversion Rate (DCS Enabled) | 20 | 105 | MSPS | |
| CLK Period—Divide-by-1 Mode (tCLK) | 9.5 | 8 | ns | |
| CLK Pulse Width High (tCH) - Divide-by-1 Mode, DCS Enabled | 6.25 | 6.65 | ns |
Key Features
- Dual, 16-bit analog-to-digital converter with sample rates of 80 MSPS, 105 MSPS, and 125 MSPS.
- Integrated output error correction logic and wide bandwidth, differential sample-and-hold analog input amplifiers.
- User-selectable input ranges and an integrated voltage reference.
- Duty cycle stabilizer to maintain performance despite ADC clock duty cycle variations.
- Flexible power-down options for significant power savings).
- Output data can be routed directly to two external 16-bit output ports, configurable to either 1.8 V CMOS or LVDS).
- Programming via a 3-wire SPI-compatible serial interface).
- Available in a 64-lead LFCSP package with an industrial temperature range of −40°C to +85°C).
Applications
The AD9268BCPZ-105 is designed to support a variety of high-performance applications, particularly in the field of communications. It is well-suited for:
- Wireless infrastructure and base stations
- Medical imaging and diagnostics
- Industrial instrumentation and control systems
- Radar and electronic warfare systems
- Other applications requiring high-speed, high-resolution ADCs with low power consumption and compact design).
Q & A
- What is the AD9268BCPZ-105?
The AD9268BCPZ-105 is a dual, 16-bit analog-to-digital converter (ADC) produced by Analog Devices Inc.
- What are the sample rates of the AD9268BCPZ-105?
The AD9268BCPZ-105 supports sample rates of 80 MSPS, 105 MSPS, and 125 MSPS.
- What is the package type of the AD9268BCPZ-105?
The AD9268BCPZ-105 is available in a 64-lead LFCSP package.
- What is the temperature range of the AD9268BCPZ-105?
The AD9268BCPZ-105 is specified over the industrial temperature range of −40°C to +85°C.
- What output modes are supported by the AD9268BCPZ-105?
The output data can be configured to either 1.8 V CMOS or LVDS.
- How is the AD9268BCPZ-105 programmed?
The AD9268BCPZ-105 is programmed using a 3-wire SPI-compatible serial interface.
- What are some key applications of the AD9268BCPZ-105?
The AD9268BCPZ-105 is used in wireless infrastructure, medical imaging, industrial instrumentation, and radar systems among others.
- What is the power consumption of the AD9268BCPZ-105?
The power consumption varies depending on the mode, but it is approximately 590 mW to 777 mW for DC input and 485 mW to 800 mW for sine wave input in CMOS output mode.
- Does the AD9268BCPZ-105 have power-down options?
Yes, the AD9268BCPZ-105 has flexible power-down options to save power when desired.
- What is the significance of the duty cycle stabilizer in the AD9268BCPZ-105?
The duty cycle stabilizer compensates for variations in the ADC clock duty cycle, ensuring excellent performance.
