Easing Data Center Burdens, SiTime Launches Differential-Ended Oscillator

This week, SiTime announced its SiT5977 Super-TCXO, a differential-ended oscillator that joins its Elite RF family as the first single-chip timing solution specifically designed to optimize AI data center efficiency.

The SiT5977 Super-TCXO measures 5 mm x 3.5 mm. Image used courtesy of SiTime

As challenges arise with high-bandwidth networking and precise synchronization within AI compute nodes, SiTime hopes its new timing solution can offer enhanced reliability and performance in a compact form factor. All About Circuits spoke with Piyush Sevalia, SiTime's executive vice president of marketing, to hear more about the new chip firsthand.

Addressing Demanding AI Compute Architectures

AI workloads are fundamentally distributed across thousands of GPUs in data center environments. As demands for low latency increase and system clock frequencies increase, data center operators must efficiently orchestrate these workloads, necessitating end-to-end network synchronization with extremely granular accuracy.

“To queue up the task for each GPU efficiently, you have to make sure that all the GPUs and the corresponding architecture are time-synchronized so that you know exactly when to send the task and when the results will come,” Sevalia explained. “It has to be synchronized within nanoseconds of accuracy.”

To this end, the SiT5977 Super-TCXO integrates high-frequency stability and low jitter into a single chip, with the product’s hallmark specification being a ±1 ppb/°C frequency slope (dF/dT) stability over temperature.

Internal block diagram of the SiT5977. Image used courtesy of SiTime

dF/dT measures how the oscillator frequency shifts with temperature changes. In high-density AI data centers, rapid thermal gradients occur due to fluctuating workloads and airflow, which could cause oscillators to drift. Therefore, precise dF/dT results in stable operation without frequency drift.

“We meet the ±1 ppb per °C spec over temperature,” Sevalia said. “This stability is critical because, during rapid thermal transients, maintaining precise synchronization ensures no performance drops or data packet loss.” 

Part of this performance is due to the SiT5977’s DualMEMS architecture, which ensures impressive thermal coupling by fabricating two resonators on the same silicon die. This design eliminates the thermal lag typical in quartz-based systems, where the physical separation between the crystal resonator and the temperature sensor leads to compensation delays.  

Architecture and Application Benefits

Traditional quartz-based timing solutions often rely on separate devices to manage jitter and stability, resulting in increased design complexity and larger board space. The SiT5977 eliminates the need for external jitter cleaners and voltage regulators by integrating these capabilities into a compact 5 mm x 3.5 mm package. 

Reducing the footprint enables system architects to allocate more board space to larger processors and additional components, optimizing processing power while maintaining synchronization across 800-G bandwidth links. This size reduction also supports the increasing trend of integrating high-performance AI compute systems into smaller, more modular architectures.

SiTime’s solution eliminates the need for external jitter cleaners. Image used courtesy of SiTime

SiTime says the space savings don’t come at the cost of performance, either. For example, its jitter is measured at 80 femtoseconds RMS across 12 kHz to 20 MHz. This directly contributes to better AI workload efficiency and lower total cost of ownership (TCO) for data centers since high-bandwidth links remain fully utilized and GPU idle times caused by data bottlenecks are reduced.

“By combining the OCXO and jitter cleaner into a single package, we’re delivering 3x better synchronization and a 4x smaller footprint,” Sevalia said. “This frees up board space, allowing for larger processors and more efficient AI workload utilization.”

The SiT5977 also offers a digital frequency control feature to add another layer of precision. Using I2C or SPI interfaces, system architects can fine-tune output frequency with ±400 ppm pull range and 0.05 ppt (5e-14) resolution. This programmability supports dynamic system adjustments for real-time corrections to maintain synchronization as workloads and environmental conditions fluctuate.

Future Implications for AI Data Centers

As data center infrastructures expand to accommodate the explosive growth in AI workloads, many in the industry will be forced to start turning toward silicon-based timing solutions. SiTime hopes that products like the SiT5977 will offer operators a means of optimizing performance, reducing energy consumption, and lowering TCO.

SiTime's CES 2025 synchronization demo of a MEMS OCXO vs. a quartz OCXO.

“The market evolves so fast that new benefits emerge over time,” Sevalia concluded. “With better jitter, stability, and tuning, there’s potential for reduced power consumption and greater efficiency, even if customers haven’t fully realized it yet.”