Overview
The Texas Instruments TSW14J57EVM is a next-generation evaluation module designed to evaluate the performance of TI's JESD204B device family, which includes high-speed analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). This module serves as a pattern generator and data capture card, enabling the capture and evaluation of data samples from ADC EVMs and the generation of test patterns for DAC EVMs. It is integrated with Intel® PSG JESD204B IP cores and supports lane speeds from 2 Gbps to 15 Gbps, with up to 16 lanes, using a single firmware build. The TSW14J57EVM is part of a complete system that includes the High-Speed Data Capture Pro Graphic User Interface (GUI) for comprehensive data capture and pattern generation capabilities.
Key Specifications
| Specification | Details |
|---|---|
| Serial Lane Speeds | Up to 15 Gbps |
| Number of Lanes | 1 to 16 |
| Memory | 16Gb DDR4 SDRAM (split into four independent 256×16, 4Gb SDRAMs) |
| Memory Operation | Quarter rate DDR4 controllers supporting up to 1200-MHz operation |
| Data Capture Capacity | Up to 1G of 16-bit samples |
| IO Standards | Supports 1.8- and 2.5-V CMOS IO standard |
| Oscillators | 100-MHz oscillator for DDR4 reference clock, optional 10-MHz oscillator for general-purpose use |
| Power Supply | Single supply voltage of +12 V DC, typical range 10V to 14V, power consumption approximately 14.5W |
| Connectors | FMC+ connector, SMA connectors, JTAG connectors |
| USB Interface | High-speed USB 3.0 to parallel converter |
Key Features
- Support for deterministic latency
- Dynamically reconfigurable transceiver data rate from 2 Gbps to 15 Gbps
- Onboard UCD90120A for power sequencing and monitoring
- Onboard Cypress CYUSB301X USB 3.0 device for JTAG and parallel interface to the FPGA
- Reference clocking for transceivers available through FMC+ port or SMAs
- Supported by TI HSDC PRO software
- ILA data and character replacement configurable through USB and JTAG
- Multiple status LEDs for indicating FPGA, DDR4, and JESD204B interface status
Applications
The TSW14J57EVM is primarily used for evaluating and testing high-speed ADCs and DACs that comply with the JESD204B standard. It is suitable for various applications in high-speed data acquisition and signal processing, such as in aerospace, defense, medical imaging, and high-performance industrial systems. The module can also be used in research and development environments to test and validate the performance of new ADC and DAC devices.
Q & A
- What is the primary function of the TSW14J57EVM?
The primary function is to evaluate the performance of TI's JESD204B device family, including high-speed ADCs and DACs, by capturing data and generating test patterns. - What are the supported serial lane speeds?
The TSW14J57EVM supports serial lane speeds up to 15 Gbps. - How many lanes does the TSW14J57EVM support?
It supports from 1 to 16 lanes. - What type of memory does the TSW14J57EVM use?
The module uses 16Gb DDR4 SDRAM, split into four independent 256×16, 4Gb SDRAMs. - What is the maximum data capture capacity of the TSW14J57EVM?
It can capture up to 1G of 16-bit samples. - What are the supported IO standards?
The TSW14J57EVM supports 1.8- and 2.5-V CMOS IO standards. - How is the TSW14J57EVM powered?
The module is powered by a single supply voltage of +12 V DC, with a typical range of 10V to 14V. - What connectors are available on the TSW14J57EVM?
The module includes an FMC+ connector, SMA connectors, and JTAG connectors. - How does the TSW14J57EVM interface with a host PC?
The module uses a high-speed USB 3.0 to parallel converter to interface with a host PC. - What software supports the TSW14J57EVM?
The module is supported by the TI HSDC PRO software.
