Overview
The TMS320LC548PGE-80 is a fixed-point digital signal processor (DSP) from Texas Instruments, based on an advanced modified Harvard architecture. This architecture features one program memory bus and three data memory buses, enabling high parallelism and simultaneous access to program instructions and data. The processor includes a 40-bit arithmetic logic unit (ALU) with a 40-bit barrel shifter and two independent 40-bit accumulators, as well as application-specific hardware logic and on-chip peripherals. The TMS320LC548 is designed for operational flexibility and speed, making it suitable for a variety of digital signal processing applications.
Key Specifications
| Specification | Details |
|---|---|
| Architecture | Advanced modified Harvard architecture with one program memory bus and three data memory buses |
| ALU | 40-bit Arithmetic Logic Unit (ALU) with 40-bit barrel shifter and two independent 40-bit accumulators |
| Multiplier | 17-× 17-Bit Parallel Multiplier coupled to a 40-Bit Dedicated Adder for non-pipelined single-cycle MAC operation |
| Memory | 192K × 16-Bit Maximum Addressable Memory Space (64K Words Program, 64K Words Data, and 64K Words I/O) |
| On-Chip Memory | Dual-Access On-Chip RAM, Single-Access On-Chip RAM, and On-Chip ROM |
| Addressing Mode | Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space |
| Peripherals | Time-Division Multiplexed (TDM) Serial Port, Two Buffered Serial Ports (BSPs), 8-Bit Parallel Host Port Interface (HPI), and One 16-Bit Timer |
| Package | 144-pin PGE TQFP and 144-pin GGU BGA |
| Clock Generator | On-Chip Phase-Locked Loop (PLL) Clock Generator with Internal Oscillator or External Clock Source |
Key Features
- Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
- Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
- Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
- Data Bus With a Bus Holder Feature and Address Bus With a Bus Holder Feature
- Single-Instruction Repeat and Block-Repeat Operations for Program Code
- Block-Memory-Move Instructions for Better Program and Data Management
- Instructions With a 32-Bit Long Word Operand and Instructions With Two- or Three-Operand Reads
- Arithmetic Instructions With Parallel Store and Parallel Load
- Conditional Store Instructions and Fast Return From Interrupt
- Software-Programmable Wait-State Generator and Programmable Bank Switching
- Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
- On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1
Applications
The TMS320LC548PGE-80 is versatile and can be used in various digital signal processing applications, including:
- Audio and speech processing
- Telecommunications, such as PSTN (Public Switched Telephone Network) interfaces
- Industrial control systems
- Medical imaging and diagnostics
- Consumer electronics, such as audio and video processing
- Automotive systems, including audio and control systems
Q & A
- What is the architecture of the TMS320LC548PGE-80?
The TMS320LC548PGE-80 is based on an advanced modified Harvard architecture with one program memory bus and three data memory buses. - What are the key components of the ALU in the TMS320LC548PGE-80?
The ALU includes a 40-bit barrel shifter and two independent 40-bit accumulators. - What type of multiplier does the TMS320LC548PGE-80 have?
The processor includes a 17-× 17-Bit Parallel Multiplier coupled to a 40-Bit Dedicated Adder for non-pipelined single-cycle MAC operation. - How much on-chip memory does the TMS320LC548PGE-80 have?
The processor has 192K × 16-Bit Maximum Addressable Memory Space, which includes 64K Words Program, 64K Words Data, and 64K Words I/O. - What types of serial ports are available on the TMS320LC548PGE-80?
The processor features one Time-Division Multiplexed (TDM) Serial Port and two Buffered Serial Ports (BSPs). - Does the TMS320LC548PGE-80 support power management features?
Yes, it supports power consumption control with IDLE1, IDLE2, and IDLE3 instructions and power-down modes. - What is the purpose of the Compare, Select, and Store Unit (CSSU) in the TMS320LC548PGE-80?
The CSSU is used for the add/compare selection of the Viterbi operator. - How many address generators and auxiliary registers does the TMS320LC548PGE-80 have?
The processor has two address generators with eight auxiliary registers and two auxiliary register arithmetic units (ARAUs). - What is the package type of the TMS320LC548PGE-80?
The processor is available in 144-pin PGE TQFP and 144-pin GGU BGA packages. - Does the TMS320LC548PGE-80 support on-chip clock generation?
Yes, it includes an on-chip Phase-Locked Loop (PLL) Clock Generator with an internal oscillator or external clock source.
