Overview
The TMS320C6746BZCEA3 is a fixed- and floating-point Digital Signal Processor (DSP) from Texas Instruments, based on the C674x DSP core. This low-power applications processor is designed to provide significantly lower power consumption compared to other members of the TMS320C6000 platform. It enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to develop devices with robust operating systems, rich user interfaces, and high processor performance. The device features a 2-level cache-based architecture, including 32KB of L1P program cache and 32KB of L1D data cache, along with 256KB of L2 unified mapped RAM/cache.
Key Specifications
| Feature | Specification |
|---|---|
| Processor Speed | 375 MHz and 456 MHz |
| DSP Core | C674x Fixed- and Floating-Point VLIW DSP |
| Instruction Set | Superset of C67x+ and C64x+ ISAs |
| MIPS and MFLOPS | Up to 3648 MIPS and 2746 MFLOPS |
| Cache Memory | 32KB L1P Program RAM/Cache, 32KB L1D Data RAM/Cache, 256KB L2 Unified Mapped RAM/Cache |
| DMA Controller | Enhanced Direct Memory Access Controller 3 (EDMA3) with 64 independent channels and 16 Quick DMA channels |
| Memory Controllers | DDR2/Mobile DDR with 16-bit bus width, up to 156 MHz for DDR2 and 150 MHz for Mobile DDR |
| External Memory Interface | Asynchronous (8/16-bit bus width) RAM, Flash, 16-bit SDRAM, NOR, NAND Flash Card Interface |
| Package | NFBGA (361 pins), 13.00 mm x 13.00 mm body size |
| Operating Temperature | -40°C to 105°C |
Key Features
- C674x Instruction Set Features: Superset of the C67x+ and C64x+ ISAs, byte-addressable (8-, 16-, 32-, and 64-bit data), 8-bit overflow protection, bit-field extract, set, clear, normalization, saturation, bit-counting, and compact 16-bit instructions.
- Cache Architecture: 32KB of L1P program RAM/cache and 32KB of L1D data RAM/cache, along with 256KB of L2 unified mapped RAM/cache.
- EDMA3 Controller: Enhanced Direct Memory Access Controller 3 with 64 independent DMA channels, 16 Quick DMA channels, and programmable transfer burst size.
- Floating-Point VLIW DSP Core: Load-store architecture with nonaligned support, 64 general-purpose registers (32-bit), six ALU (32- and 40-bit) functional units, supports 32-bit integer, single precision (SP), and double precision (DP) floating-point operations.
- Programmable Real-Time Unit Subsystem (PRUSS): Two independent programmable real-time unit (PRU) cores with 32-bit load-store RISC architecture, 4KB of instruction RAM per core, and 512 bytes of data RAM per core.
- USB 2.0 OTG Port: Integrated PHY, supports high-, full-, and low-speed client and host modes.
- Audio and Serial Ports: One multichannel audio serial port (McASP) and two multichannel buffered serial ports (McBSPs), supporting TDM, I2S, and similar formats.
- Ethernet MAC (EMAC): IEEE 802.3 compliant, supports MII and RMII interfaces, and management data I/O (MDIO) module.
- Video Port Interface (VPIF): Flexible video I/O port supporting various video capture and display formats.
Applications
- Currency Inspection: Used in systems that require high-performance image processing and analysis.
- Biometric Identification: Suitable for applications involving facial recognition, fingerprint analysis, and other biometric data processing.
- Machine Vision (Low-End): Ideal for low-end machine vision applications that require real-time image processing and analysis).
Q & A
- What is the TMS320C6746BZCEA3 processor based on?
The TMS320C6746BZCEA3 is based on the C674x DSP core.
- What are the key features of the C674x instruction set?
The C674x instruction set is a superset of the C67x+ and C64x+ ISAs, featuring byte-addressable data, 8-bit overflow protection, bit-field operations, and compact 16-bit instructions.
- What is the cache architecture of the TMS320C6746BZCEA3?
The device features a 2-level cache architecture with 32KB of L1P program cache, 32KB of L1D data cache, and 256KB of L2 unified mapped RAM/cache.
- What is the role of the EDMA3 controller in the TMS320C6746BZCEA3?
The EDMA3 controller provides enhanced direct memory access with 64 independent DMA channels, 16 Quick DMA channels, and programmable transfer burst size.
- What floating-point operations are supported by the TMS320C6746BZCEA3?
The device supports 32-bit integer, single precision (SP), and double precision (DP) floating-point operations, including up to four SP additions per clock and four DP additions every two clocks.
- What is the Programmable Real-Time Unit Subsystem (PRUSS) in the TMS320C6746BZCEA3?
The PRUSS includes two independent programmable real-time unit (PRU) cores with 32-bit load-store RISC architecture, each having 4KB of instruction RAM and 512 bytes of data RAM.
- What are the key peripherals of the TMS320C6746BZCEA3?
The device includes peripherals such as USB 2.0 OTG, multichannel audio serial port (McASP), multichannel buffered serial ports (McBSPs), Ethernet MAC (EMAC), and a video port interface (VPIF).
- What are some common applications of the TMS320C6746BZCEA3?
Common applications include currency inspection, biometric identification, and low-end machine vision.
- What is the operating temperature range of the TMS320C6746BZCEA3?
The operating temperature range is -40°C to 105°C.
- What is the package type and pin count of the TMS320C6746BZCEA3?
The device is packaged in an NFBGA with 361 pins and a body size of 13.00 mm x 13.00 mm.
