Overview
The TMS320C6742EZCE2 is a fixed- and floating-point Digital Signal Processor (DSP) from Texas Instruments, based on the C674x DSP core. This device is designed as a low-power applications processor, offering significant power savings compared to other members of the TMS320C6000 platform. It is tailored for original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to develop devices with robust operating systems, rich user interfaces, and high processor performance. The DSP features a 2-level cache-based architecture, enhancing performance and efficiency.
Key Specifications
| Specification | Details |
|---|---|
| Processor Core | 200-MHz C674x Fixed- and Floating-Point VLIW DSP |
| Instruction Set | Superset of the C67x+ and C64x+ ISAs, up to 1600 MIPS and 1200 MFLOPS |
| Cache Memory | 32KB L1P Program RAM/Cache, 32KB L1D Data RAM/Cache, 64KB L2 Unified Mapped RAM/Cache |
| DMA Controller | Enhanced Direct Memory Access Controller 3 (EDMA3) with 64 independent DMA channels and 16 quick DMA channels |
| Memory Interfaces | DDR2/mDDR Memory Controller, EMIFA, NOR, NAND, 16-bit SDRAM |
| Serial Interfaces | UART, SPI, I2C, McASP, McBSP |
| Timers and Counters | Two 64-bit general-purpose timers, one 64-bit general-purpose or watchdog timer |
| Pulse Width Modulators | Two enhanced high-resolution pulse width modulators (eHRPWM) |
| Capture Modules | Three 32-bit enhanced capture (eCAP) modules |
| Package | 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) |
| Operating Voltage | 1.8-V or 3.3-V LVCMOS I/Os |
Key Features
- High Performance: Up to 1600 MIPS and 1200 MFLOPS, with support for 32-bit integer, single precision (SP), and double precision (DP) floating-point operations.
- Cache Architecture: 2-level cache with 32KB L1P and L1D caches, and a 64KB L2 unified cache.
- Enhanced DMA: EDMA3 with 64 independent DMA channels and 16 quick DMA channels.
- Rich Peripheral Set: Includes UART, SPI, I2C, McASP, McBSP, eHRPWM, eCAP, and GPIO.
- Memory Interfaces: Supports DDR2/mDDR, EMIFA, NOR, NAND, and 16-bit SDRAM.
- Low Power Consumption: Designed for low-power applications.
- Development Tools: Includes C compilers, DSP assembly optimizer, and a Windows debugger interface.
Applications
- Currency Inspection: Used in systems for detecting and verifying currency.
- Biometric Identification: Employed in biometric systems for identification purposes.
- Machine Vision (Low-End): Suitable for low-end machine vision applications.
Q & A
- What is the core frequency of the TMS320C6742EZCE2?
The core frequency is 200 MHz.
- What type of cache architecture does the TMS320C6742EZCE2 use?
The device uses a 2-level cache architecture with 32KB L1P and L1D caches, and a 64KB L2 unified cache.
- What is the EDMA3 controller capable of?
The EDMA3 controller has 64 independent DMA channels and 16 quick DMA channels.
- What memory interfaces are supported by the TMS320C6742EZCE2?
The device supports DDR2/mDDR, EMIFA, NOR, NAND, and 16-bit SDRAM.
- What are the key serial interfaces available on the TMS320C6742EZCE2?
The device includes UART, SPI, I2C, McASP, and McBSP interfaces.
- How many timers does the TMS320C6742EZCE2 have?
The device has two 64-bit general-purpose timers and one 64-bit general-purpose or watchdog timer.
- What is the purpose of the eHRPWM and eCAP modules?
The eHRPWM modules are used for high-resolution pulse width modulation, and the eCAP modules are used for enhanced capture or auxiliary pulse width modulation.
- What is the package type of the TMS320C6742EZCE2?
The device is packaged in a 361-Ball Pb-Free Plastic Ball Grid Array (PBGA).
- What are the operating voltage options for the TMS320C6742EZCE2?
The device operates with 1.8-V or 3.3-V LVCMOS I/Os.
- What development tools are available for the TMS320C6742EZCE2?
The device is supported by C compilers, a DSP assembly optimizer, and a Windows debugger interface.
