Overview
The DP83867ERGZ-S-EVM is a reference design board developed by Texas Instruments, designed to support the DP83867ERGZ Ethernet PHY (Physical Layer) device. This evaluation module (EVM) is compliant with the IEEE 802.3 standard and supports 1000BASE-T, 100BASE-TX, and 10BASE-T Ethernet speeds. It features an SGMII MAC interface, making it suitable for various industrial and networking applications. The board includes onboard status LEDs, 5V connectors with onboard LDOs, and is JTAG accessible, facilitating comprehensive system evaluation and development.
Key Specifications
| Specification | Details |
|---|---|
| Ethernet Speeds | 1000BASE-T, 100BASE-TX, 10BASE-T |
| IEEE Compliance | IEEE 802.3 |
| MAC Interface | SGMII |
| Power Supply | Single 5V DC jack with onboard LDOs for 2.5V and 1.0V voltage rails |
| Clock Options | 25MHz crystal, 25MHz oscillator, or external 25MHz reference clock |
| LED Indicators | Three onboard status LEDs for link, speed, and activity |
| Serial Management Interface | MDIO/MDC |
| JTAG Interface | JTAG accessible |
| Low Power Modes | Active Sleep, Passive Sleep, IEEE Power Down, Deep Power Down |
| Wake-on-LAN | Supported |
| IEEE 1588 Time Stamp | Supported |
| I/O Voltage Range | 1.8V, 2.5V, 3.3V |
Key Features
- 1000BASE-T, 100BASE-TX, and 10BASE-T IEEE 802.3 compliance
- SGMII MAC interface support
- Serial management interface (MDIO/MDC) for accessing PHY registers
- Three onboard status LEDs for link, speed, and activity indications
- JTAG interface for debugging and testing
- Low power modes: Active Sleep, Passive Sleep, IEEE Power Down, and Deep Power Down
- Wake-on-LAN and Start of Frame Detect IEEE 1588 Time Stamp capabilities
- Configurable I/O voltage range: 1.8V, 2.5V, and 3.3V
- Support for external power supplies and 4-level straps for system configurations
Applications
The DP83867ERGZ-S-EVM is designed for various industrial and networking applications, including but not limited to:
- Industrial Ethernet systems
- Network infrastructure devices
- Embedded systems requiring Ethernet connectivity
- Development and testing of Ethernet-based products
- Integration with FPGA or ASIC designs, such as those using Xilinx UltraScale+ processors
Q & A
- What are the supported Ethernet speeds of the DP83867ERGZ-S-EVM?
The DP83867ERGZ-S-EVM supports 1000BASE-T, 100BASE-TX, and 10BASE-T Ethernet speeds.
- Is the DP83867ERGZ-S-EVM compliant with any IEEE standards?
Yes, it is compliant with the IEEE 802.3 standard.
- What type of MAC interface does the DP83867ERGZ-S-EVM support?
The DP83867ERGZ-S-EVM supports the SGMII MAC interface.
- How is the power supply configured on the DP83867ERGZ-S-EVM?
The board is powered by a single 5V DC jack with onboard LDOs providing 2.5V and 1.0V voltage rails. It also supports external power supplies.
- What clock options are available for the DP83867ERGZ-S-EVM?
The board supports a 25MHz crystal, a 25MHz oscillator, or an external 25MHz reference clock.
- Does the DP83867ERGZ-S-EVM support Wake-on-LAN and IEEE 1588 Time Stamp?
Yes, it supports both Wake-on-LAN and Start of Frame Detect IEEE 1588 Time Stamp.
- What are the low power modes available on the DP83867ERGZ-S-EVM?
The available low power modes include Active Sleep, Passive Sleep, IEEE Power Down, and Deep Power Down.
- Can the I/O voltage be configured on the DP83867ERGZ-S-EVM?
Yes, the I/O voltage can be configured to 1.8V, 2.5V, or 3.3V.
- Is the DP83867ERGZ-S-EVM JTAG accessible?
Yes, the board is JTAG accessible for debugging and testing purposes.
- What is the purpose of the serial management interface on the DP83867ERGZ-S-EVM?
The serial management interface (MDIO/MDC) allows access to PHY registers for additional features and configurations.
