Overview
The CDCLVD1216RGZT, produced by Texas Instruments, is a 2:16 low additive jitter LVDS (Low Voltage Differential Signaling) buffer. This device is designed to distribute one of two selectable clock inputs to 16 pairs of differential LVDS clock outputs, ensuring minimal skew and low jitter. It operates within a wide frequency range, making it suitable for various high-speed clock distribution applications.
The CDCLVD1216 supports universal inputs that can accept LVDS, LVPECL, or LVCMOS signals, and it is packaged in a compact 48-pin QFN (Quad Flat No-Lead) package. The device is characterized over an industrial temperature range of –40°C to 85°C and features ESD protection exceeding 3 kV HBM and 1 kV CDM.
Key Specifications
| Parameter | Min | Max | Unit | |
|---|---|---|---|---|
| Supply Voltage Range (VCC) | 2.375 | 2.5 | 2.625 | V |
| Ambient Temperature Range (TA) | –40 | 85 | °C | |
| Input Frequency (fIN) | 800 | MHz | ||
| Differential Input Voltage Peak-to-Peak (VIN, DIFF) | 0.3 | 1.6 | VPP | |
| Output Skew (tSK, O) | 55 | ps | ||
| Random Additive Jitter (tRJIT) | 0.3 | ps RMS (10 kHz – 20 MHz) | ||
| Output Rise/Fall Time (tR/tF) | 50 | 300 | ps | |
| Static Supply Current (ICCSTAT) | 17 | 28 | mA | |
| Supply Current at 100 MHz (ICC100) | 107 | 140 | mA | |
| Supply Current at 800 MHz (ICC800) | 147 | 180 | mA |
Key Features
- 2:16 differential buffer distributing one of two selectable clock inputs to 16 pairs of differential LVDS clock outputs.
- Low additive jitter: <300 fs RMS in the 10 kHz to 20 MHz range.
- Low output skew of 55 ps (max).
- Universal inputs accepting LVDS, LVPECL, or LVCMOS signals.
- Selectable clock inputs through control pin.
- 16 LVDS outputs compliant with ANSI EIA/TIA-644A standard.
- Clock frequency up to 800 MHz.
- Device power supply range: 2.375–2.625V.
- LVDS reference voltage (VAC_REF) available for capacitive coupled inputs.
- Industrial temperature range: –40°C to 85°C.
- Packaged in a 7mm × 7mm 48-pin QFN (RGZ) package.
- ESD protection exceeding 3 kV HBM and 1 kV CDM.
Applications
- Telecommunications/Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General Purpose Clocking
Q & A
- What is the primary function of the CDCLVD1216?
The CDCLVD1216 is a 2:16 differential buffer that distributes one of two selectable clock inputs to 16 pairs of differential LVDS clock outputs.
- What types of input signals can the CDCLVD1216 accept?
The CDCLVD1216 can accept LVDS, LVPECL, or LVCMOS input signals.
- What is the maximum clock frequency supported by the CDCLVD1216?
The CDCLVD1216 supports clock frequencies up to 800 MHz.
- What is the typical additive jitter of the CDCLVD1216?
The CDCLVD1216 has a typical additive jitter of less than 300 fs RMS in the 10 kHz to 20 MHz range.
- What is the output skew of the CDCLVD1216?
The output skew of the CDCLVD1216 is 55 ps (max).
- What is the operating temperature range of the CDCLVD1216?
The CDCLVD1216 operates over an industrial temperature range of –40°C to 85°C.
- What is the package type and size of the CDCLVD1216?
The CDCLVD1216 is packaged in a 7mm × 7mm 48-pin QFN (RGZ) package.
- What level of ESD protection does the CDCLVD1216 offer?
The CDCLVD1216 offers ESD protection exceeding 3 kV HBM and 1 kV CDM.
- How should the LVDS outputs of the CDCLVD1216 be terminated for signal integrity?
The LVDS outputs should be terminated with a 100 Ω resistor between the outputs on the receiver end, either using dc-coupled or ac-coupled termination.
- What are some common applications of the CDCLVD1216?
The CDCLVD1216 is commonly used in telecommunications/networking, medical imaging, test and measurement equipment, wireless communications, and general purpose clocking.
