Overview
The CDCDB803RSLR is a high-performance, 8-output clock buffer designed by Texas Instruments to meet the stringent requirements of PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. This device is DB800ZL-compliant and also meets or exceeds the parameters specified in the DB2000Q specification. It is packaged in a 6-mm × 6-mm, 48-pin VQFN package, making it suitable for a variety of server and storage applications. The CDCDB803RSLR features low additive jitter, low propagation delay, and extensive control options via SMBus and hardware output enable pins, ensuring reliable and precise clock distribution.
Key Specifications
| Parameter | Value | Unit |
|---|---|---|
| Number of Outputs | 8 | - |
| Output Type | LP-HCSL differential clock output | - |
| Output Termination | Programmable 85-Ω or 100-Ω differential | - |
| Additive Phase Jitter (PCIe Gen 6) | 20 fs, RMS (maximum) | fs |
| Additive Phase Jitter (PCIe Gen 5) | 25 fs, RMS (maximum) | fs |
| Additive Phase Jitter (DB2000Q) | 38 fs, RMS (maximum) | fs |
| Output-to-Output Skew | < 50 ps | ps |
| Input-to-Output Delay | < 3 ns | ns |
| Core and IO Supply Voltage | 3.3 V ± 5% | V |
| Current Consumption (Active Mode) | 72 mA (maximum) | mA |
| Package Type | 48-pin VQFN | - |
| Package Size | 6-mm × 6-mm | mm |
Key Features
- 8 LP-HCSL outputs with programmable integrated 85-Ω or 100-Ω differential output terminations
- 8 hardware output enable (OE#) controls for individual output management
- Low additive phase jitter: 20 fs (PCIe Gen 6), 25 fs (PCIe Gen 5), and 38 fs (DB2000Q)
- Support for Common Clock (CC) and Individual Reference (IR) architectures and spread spectrum compatibility
- Output-to-output skew of less than 50 ps and input-to-output delay of less than 3 ns
- Fail-safe input operation and programmable output slew rate control
- SMBus interface with 9 selectable SMBus addresses for configuration and control
- Hardware-controlled low power mode (PD#) with reduced current consumption
Applications
- Microserver and tower server
- Storage area network and host bus adapter card
- Network attached storage
- Hardware accelerator
- Rack server
Q & A
- What is the CDCDB803RSLR used for?
The CDCDB803RSLR is used for distributing reference clocks for PCIe Gen 1-6, QPI, UPI, SAS, and SATA interfaces in various server and storage applications.
- How many outputs does the CDCDB803RSLR have?
The CDCDB803RSLR has 8 LP-HCSL differential clock outputs.
- What are the programmable output terminations available on the CDCDB803RSLR?
The CDCDB803RSLR supports programmable integrated 85-Ω or 100-Ω differential output terminations.
- What is the additive phase jitter of the CDCDB803RSLR for PCIe Gen 6?
The additive phase jitter for PCIe Gen 6 is 20 fs, RMS (maximum).
- Does the CDCDB803RSLR support SMBus interface?
Yes, the CDCDB803RSLR supports an SMBus interface with 9 selectable SMBus addresses.
- How is the power mode controlled on the CDCDB803RSLR?
The power mode is controlled via the CKPWRGD_PD# pin, which allows for hardware-controlled low power mode.
- What is the package type and size of the CDCDB803RSLR?
The CDCDB803RSLR is packaged in a 48-pin VQFN package with a size of 6-mm × 6-mm.
- What are some of the key applications of the CDCDB803RSLR?
Key applications include microservers, tower servers, storage area networks, host bus adapter cards, network attached storage, hardware accelerators, and rack servers.
- Does the CDCDB803RSLR support fail-safe input operation?
Yes, the CDCDB803RSLR is designed to support fail-safe input operation, allowing inputs to be driven before VDD is applied without damaging the device.
- How is the output slew rate controlled on the CDCDB803RSLR?
The output slew rate is programmable, allowing for customized output characteristics.
