Overview
The CDCDB2000NPPR is a 20-output LP-HCSL clock buffer designed by Texas Instruments. It is compliant with the DB2000QL specification and is capable of distributing the reference clock for PCIe Gen 1 to Gen 5, as well as for QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. This device is packaged in a 6-mm × 6-mm TLGA/GQFN package with 80 leads. The CDCDB2000 allows for the buffering and replication of a single clock source to up to 20 individual outputs, making it highly versatile for various high-speed applications.
Key Specifications
| Parameter | Value | Unit |
|---|---|---|
| Package | TLGA (NPP) | - |
| Pins | 80 | - |
| Operating Temperature Range | -40 to 85 | °C |
| Core and IO Supply Voltages | 3.135 to 3.465 | V |
| Power Consumption | < 600 | mW |
| Additive Phase Jitter after DB2000QL Filter | < 0.08 | ps rms |
| Cycle-to-Cycle Jitter | < 50 | ps |
| Output-to-Output Skew | < 50 | ps |
| Input-to-Output Delay | < 3 | ns |
| Junction-to-Ambient Thermal Resistance | 32.7 | °C/W |
Key Features
- 20 LP-HCSL outputs with integrated 85-Ω output terminations
- 8 hardware output enable (OE#) controls
- Additive phase jitter after DB2000QL filter: < 0.08ps rms
- Supports PCIe Gen 4 and Gen 5 Common Clock (CC) and Individual Reference (IR) architectures
- Spread spectrum-compatible
- Cycle-to-cycle jitter: < 50 ps
- Output-to-output skew: < 50 ps
- Input-to-output delay: < 3 ns
- 3.3-V core and IO supply voltages
- Hardware-controlled low power mode (PD#)
- Side-Band Interface (SBI) for output control in PD# mode
- 9 selectable SMBus addresses
Applications
- Microserver and tower server
- Storage area network and host bus adapter card
- Network attached storage
- Hardware accelerator
Q & A
- What is the CDCDB2000NPPR used for?
The CDCDB2000NPPR is used for distributing the reference clock for PCIe Gen 1 to Gen 5, QPI, UPI, SAS, and SATA interfaces.
- What package type does the CDCDB2000NPPR come in?
The CDCDB2000NPPR is packaged in a 6-mm × 6-mm TLGA/GQFN package with 80 leads.
- What are the core and IO supply voltages for the CDCDB2000NPPR?
The core and IO supply voltages are 3.135 to 3.465 V.
- What is the additive phase jitter after the DB2000QL filter?
The additive phase jitter after the DB2000QL filter is less than 0.08 ps rms.
- Does the CDCDB2000NPPR support spread spectrum clocking?
Yes, the CDCDB2000NPPR is spread spectrum-compatible.
- What is the cycle-to-cycle jitter of the CDCDB2000NPPR?
The cycle-to-cycle jitter is less than 50 ps.
- How many SMBus addresses can the CDCDB2000NPPR support?
The CDCDB2000NPPR supports 9 selectable SMBus addresses.
- What is the power consumption of the CDCDB2000NPPR?
The power consumption is less than 600 mW.
- What are the typical applications of the CDCDB2000NPPR?
The typical applications include microservers, tower servers, storage area networks, host bus adapter cards, network attached storage, and hardware accelerators.
- How does the CDCDB2000NPPR manage low power mode?
The CDCDB2000NPPR has a hardware-controlled low power mode (PD#) and a Side-Band Interface (SBI) for output control in PD# mode.
