Overview
The SPC582B60E1MH00Y is a 32-bit microcontroller from STMicroelectronics, part of the SPC58 2B line family. It is built on the legacy of the SPC5x products and introduces new features to meet future automotive requirements, such as ASIL-B classification, a high number of ISO CAN-FD channels, and significant power and performance improvements (MIPS per mW).
This microcontroller features a high-performance e200z2 single core with a 32-bit power architecture technology CPU, operating at a core frequency of up to 80 MHz. It includes variable length encoding (VLE), floating point, and end-to-end error correction capabilities. The device is AEC-Q100 qualified, ensuring it meets stringent automotive safety and reliability standards.
Key Specifications
| Parameter | Value |
|---|---|
| Device Core | Power Architecture |
| No. of Bits | 32-bit |
| CPU Speed | 80 MHz |
| Program Memory Size | 1 MB (1024 KB code flash + 64 KB data flash) |
| No. of Pins | 64 Pins |
| No. of I/O's | 48 I/O's |
| IC Case / Package | TQFP-EP |
| Interfaces | CAN, I2C, SPI, UART |
| RAM Memory Size | 96 KB |
| ADC Channels | 18 Channels (up to 27 channels with enhanced diagnosis feature) |
| ADC Resolution | 10-bit, 12-bit |
| Supply Voltage Min | 1.14 V |
| Supply Voltage Max | 1.26 V |
| Operating Temperature Min | -40°C |
| Operating Temperature Max | 125°C |
| IC Mounting | Surface Mount |
| MCU Family | SPC5 |
| MCU Series | SPC582Bxx |
| Qualification | AEC-Q100 |
| MSL | MSL 3 - 168 hours |
Key Features
- High Performance CPU: e200z2 single core with 32-bit power architecture technology, operating at up to 80 MHz.
- Memory and Storage: 1088 KB on-chip flash memory (1024 KB code flash + 64 KB data flash) and 96 KB on-chip general-purpose SRAM.
- Communication Interfaces: 6 LINFlexD modules, 4 DSPI modules, and 7 MCAN interfaces with ISO CAN-FD support.
- Safety Features: Comprehensive ASIL-B safety concept, FCCU for failure notifications, MEMU for memory error management, and CRC unit with end-to-end ECC logic.
- ADC and I/O: Up to 27 enhanced 12-bit SAR analog-to-digital converter channels and up to 32 timed I/O channels with 16-bit counter resolution.
- Power Management: On-chip voltage regulator for 1.2 V core logic supply and advanced flexible supply scheme.
- Debug and Trace: Nexus Class 3 debug and trace interface).
Applications
The SPC582B60E1MH00Y microcontroller is primarily designed for automotive applications, particularly where high performance, reliability, and safety are critical. It is suitable for various automotive systems, including:
- Powertrain control systems
- Body control modules
- Advanced driver assistance systems (ADAS)
- Infotainment and telematics systems
- Safety-critical systems requiring ASIL-B compliance
Q & A
- What is the core architecture of the SPC582B60E1MH00Y microcontroller?
The SPC582B60E1MH00Y features a 32-bit power architecture technology CPU with an e200z2 single core).
- What is the maximum operating frequency of the SPC582B60E1MH00Y?
The maximum operating frequency is 80 MHz).
- How much on-chip flash memory does the SPC582B60E1MH00Y have?
The device has 1088 KB of on-chip flash memory (1024 KB code flash + 64 KB data flash)).
- What are the key safety features of the SPC582B60E1MH00Y?
It includes ASIL-B safety concept, FCCU, MEMU, and CRC unit with end-to-end ECC logic).
- What communication interfaces are available on the SPC582B60E1MH00Y?
The device features 6 LINFlexD modules, 4 DSPI modules, and 7 MCAN interfaces with ISO CAN-FD support).
- What is the operating temperature range of the SPC582B60E1MH00Y?
The operating temperature range is from -40°C to 125°C).
- Is the SPC582B60E1MH00Y AEC-Q100 qualified?
Yes, the SPC582B60E1MH00Y is AEC-Q100 qualified).
- What type of package does the SPC582B60E1MH00Y come in?
The device comes in a TQFP-EP package).
- How many ADC channels does the SPC582B60E1MH00Y have?
The device has up to 27 enhanced 12-bit SAR analog-to-digital converter channels).
- What is the purpose of the FCCU in the SPC582B60E1MH00Y?
The FCCU is for the collection and reaction to failure notifications).
